ST STM32F405 User Manual

LCD-TFT controller (LTDC) RM0090
500/1749 RM0090 Rev 18
16.7.11 LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR)
This register defines the position of the line interrupt. The line value to be programmed
depends on the timings parameters. Refer to Figure 82.
Address offset: 0x40
Reset value: 0x0000 0000
16.7.12 LTDC Current Position Status Register (LTDC_CPSR)
Address offset: 0x44
Reset value: 0x0000 0000
Bits 31:24 Reserved, must be kept at reset value
Bit 3 CRRIF: Clears Register Reload Interrupt Flag
0: No effect
1: Clears the RRIF flag in the LTDC_ISR register
Bit 2 CTERRIF: Clears the Transfer Error Interrupt Flag
0: No effect
1: Clears the TERRIF flag in the LTDC_ISR register.
Bit 1 CFUIF: Clears the FIFO Underrun Interrupt flag
0: No effect
1: Clears the FUDERRIF flag in the LTDC_ISR register.
Bit 0 CLIF: Clears the Line Interrupt Flag
0: No effect
1: Clears the LIF flag in the LTDC_ISR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LIPOS[10:0]
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:11 Reserved, must be kept at reset value
Bits 10:0 LIPOS[10:0]: Line Interrupt Position
These bits configure the line interrupt position
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CXPOS[15:0]
r rrrr r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYPOS{15;0]
r rrrr r r r r r r r r r r r

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English