Agilent Technologies E5071C - Page 913

E5071C
1140
Bit
Position
Name Description
0
Channel 15, 16 Bandwidth
test summary
(questionable bandwidth
limit extra status register
summary)
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
extra status event register is
set to "1."
1
Channel 1 Bandwidth Test
Fail (questionable
bandwidth limit channel 1
status register summary)
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 1 status event
register is set to "1."
2
Channel 2 Bandwidth Test
Fail (questionable
bandwidth limit channel 2
status register summary)
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 2 status event
register is set to "1."
3
Channel 3 Bandwidth Test
Fail (questionable
bandwidth limit channel 3
status register summary)
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 3 status event
register is set to "1."
4
Channel 4 Bandwidth Test
Fail (questionable
bandwidth limit channel 4
status register summary)
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 4 status event
register is set to "1."
5
Channel 5 Bandwidth Test
Fail (questionable
bandwidth limit channel 5
status register summary)
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 5 status event
register is set to "1."
6
Channel 6 Bandwidth Test
Fail (questionable
bandwidth limit channel 6
status register summary)
Set to "1" while one of the
enabled bits in the
questionable bandwidth limit
channel 6 status event
register is set to "1."