Programming
1123
Status Register for Limit Test (channel)
Status Bit Definitions of the Questionable Limit Status Condition
Register
Bit
Position
Name Description
0
Channel 15, 16 Limit Test
summary (questionable
limit extra status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit extra
status event register is set to
"1."
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