Agilent Technologies E5071C

E5071C
1124
1
Channel 1 Limit Test Fail
(questionable limit
channel 1 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 1
status event register is set to
"1."
2
Channel 2 Limit Test Fail
(questionable limit
channel 2 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 2
status event register is set to
"1."
3
Channel 3 Limit Test Fail
(questionable limit
channel 3 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 3
status event register is set to
"1."
4
Channel 4 Limit Test Fail
(questionable limit
channel 4 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 4
status event register is set to
"1."
5
Channel 5 Limit Test Fail
(questionable limit
channel 5 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 5
status event register is set to
"1."
6
Channel 6 Limit Test Fail
(questionable limit
channel 6 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 6
status event register is set to
"1."
7
Channel 7 Limit Test Fail
(questionable limit
channel 7 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 7
status event register is set to
"1."
8
Channel 8 Limit Test Fail
(questionable limit
channel 8 status register
Set to "1" while one of the
enabled bits in the
questionable limit channel 8