Agilent Technologies E5071C

Programming
1125
summary) status event register is set to
"1."
9
Channel 9 Limit Test Fail
(questionable limit
channel 9 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 9
status event register is set to
"1."
10
Channel 10 Limit Test Fail
(questionable limit
channel 10 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 10
status event register is set to
"1."
11
Channel 11 Limit Test Fail
(questionable limit
channel 11 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 11
status event register is set to
"1."
12
Channel 12 Limit Test Fail
(questionable limit
channel 12 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 12
status event register is set to
"1."
13
Channel 13 Limit Test Fail
(questionable limit
channel 13 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 13
status event register is set to
"1."
14
Channel 14 Limit Test Fail
(questionable limit
channel 14 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 14
status event register is set to
"1."
15 Not used Always 0
Issuing the *CLS command will clear all bits from the questionable limit
status event register.