E5071C
1126
Status Bit Definitions of the Questionable Limit Extra Status
Condition Register
Bit
Position
Name Description
0 Not used Always 0
1
Channel 15 Limit Test Fail
(questionable limit
channel 15 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 15
status event register is set to
"1."
2
Channel 16 Limit Test Fail
(questionable limit
channel 16 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel 16
status event register is set to
"1."
3 - 15 Not used Always 0
Issuing the *CLS command will clear all bits from the questionable limit
extra status event register.
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