AMD Elan SC520 - Page 415

Élan™SC520 Microcontroller User’s Manual Index-1
INDEX
Numerics
32KXTAL2–32KXTAL1 signals
description, 2-10
usage, 5-3, 5-8
33MXTAL2–33MXTAL1 signals
description, 2-10
usage, 2-7, 5-3
A
A10–A8 bit field, 15-18
a20 gate support, 6-8
A20G_CTL bit field, 6-8
GP bus.
See general-purpose (GP) bus.
AD31–AD0 signals
description, 2-6
usage, 2-7, 9-3, 9-9
ADDDECCTL register, 4-2
address buses
general-purpose (GP) bus address bus, 2-6
PCI address bus, 2-6
ROM/Flash controller address bus, 2-6
SDRAM controller address bus, 2-5
shared buses, 13-10
Address Decode Control (ADDDECCTL) register
function, 4-2, 20-6, 21-3, 24-2
usage, 3-21, 4-12, 4-14, 4-19, 20-5, 24-11
address mapping
bus master address spaces (table), 4-3
cacheability control, 4-15, 4-19
code execution control, 4-15, 4-19
configuration, 4-14
buses, 4-4
chip select for noncontiguous memory or
I/O, 4-15
chip selects, 4-4
external memory, 4-4
external super I/O chip, 4-15
GP bus peripheral space, 4-15
memory regions above DOS application
space, 4-16
PCI bus devices, 4-17
ROM/Flash space, 4-14
Windows® compatibility, 4-16
configuration register access, 4-19
I/O map (figure), 4-11
I/O space, 4-10
Configuration Base Address register, 4-11
GP bus I/O region, 4-14
PC/AT-compatible I/O peripherals region, 4-12
PCI configuration space, 4-11
PCI I/O space, 4-12
initialization, 4-20
interrupts, 4-17
memory and I/O space summary (table), 4-4
memory map (figure), 4-7
memory space, 4-7
GP bus memory space, 4-9
integrated memory-mapped peripherals, 4-10
memory-mapped configuration region (MMCR)
space, 4-9
PCI bus memory space, 4-9
SDRAM space, 4-8
operation, 4-3
ositive address decoding, 4-9
PC/AT peripherals I/O map (table), 4-13
positive address decoding, 3-13
positive address decoding (example), 3-14, 4-15
Programmable Address Region (PAR) registers, 4-5
PAR register format (figure), 4-6
registers, 4-2
software considerations, 4-17
write protection violation, 4-17, 4-19
write-protection violation, 4-15
AEOI bit field, 15-18
AINIT bit field, 14-14
ALM_AM_PM bit field, 20-8
ALM_INT_ENB bit field, 20-9
ALT_CMP bit field, 17-4, 17-5
AM_PM bit field, 20-8
Am486® CPU
instruction set, xxiv
Am5
x
86 CPU Control (CPUCTL) register
function, 5-6, 7-1, 24-2
usage, 5-7, 7-3–7-4
Am5
x
86® CPU
block diagram (figure), 7-2
bus arbitration, 8-3
cache
behavior during clock speed changes, 7-4
configuration options (table), 7-4
flushing, 24-11
memory management, 7-4
performance considerations, 24-12
clocking considerations, 7-4, 8-7