Index
Index-2 Élan™SC520 Microcontroller User’s Manual
CPU core identification, 3-7
CPU PLL stabilization time, 7-4
CPU speed, 3-7
documentation, xxiv
floating point unit (FPU), 7-3
initialization, 7-5
hard CPU reset, 7-5
soft CPU reset, 6-7, 7-5
interrupts, 7-5
latency, 7-5
operation, 7-3
registers, 7-1
AMDebug Disable signal.
See
AMDEBUG_DIS signal.
AMDebug Technology RX/TX Interrupt Mapping
(ICEMAP) register
function, 15-5
AMDEBUG_DIS signal
description, 2-13
usage, 26-2
AMDebug™ technology
block diagram (figure), 26-2
on-chip trace cache, 26-6
operation, 26-6
signal descriptions, 2-12
software architecture (figure), 26-2
software performance profiling, 26-7
system design, 26-2
12-pin connector format (figure), 26-3
20-pin serial connector format (figure), 26-4
connecting the AMDebug port, 26-2
connector pins (table), 26-3
locating the target connector (figure), 26-5
target connector mechanical specifications, 26-4
Analog Ground signal.
See
GND_ANLG signal.
Analog Power Supply signal.
See
VCC_ANLG signal.
applications.
See
Élan™SC520 microcontroller.
Arbiter Priority Control (ARBPRICTL) register
function, 8-2
usage, 8-8, 8-20, 8-22
arbitration.
See
system arbitration.
ARBPRICTL register, 8-2
ATTR bit field, 3-10, 3-12, 4-5, 4-15
B
BA1–BA0 signals
control, 10-10, 10-19
description, 2-5
Backup Battery Sense signal.
See
BBATSEN signal.
Bank Address signals.
See
BA1–BA0 signals.
BBATSEN signal
description, 2-14
usage, 6-7, 20-3, 20-4, 20-7, 20-11
BI bit field, 21-8
BIOS.
See
system initialization.
bit fields
A10–A8, 15-18
A20G_CTL, 6-8
AEOI, 15-18
AINIT, 14-14
ALM_AM_PM, 20-8
ALM_INT_ENB, 20-9
ALT_CMP, 17-4, 17-5
AM_PM, 20-8
ATTR,3-10,3-12,4-5,4-15
BI, 21-8
BNKx_BNK_CNT, 10-15, 10-15
BNKx_COLWDTH, 10-15, 10-15
BSY, 22-7
BUS_MAS, 9-11
BUS_NUM, 9-10
BUS_PARK_SEL, 8-10, 8-22
CACHE_WR_MODE, 7-4, 8-6
CAS_LAT, 10-20, 10-31
CH3_ALT_SIZE, 14-21
CLK_INV_ENB, 22-5
CLK_PIN_DIR, 5-3, 5-9, 16-1, 16-6, 16-7
CLK_PIN_ENB, 5-9
CLK_SEL, 5-8, 22-7
CLK_SRC, 21-10
CLK_TST_SEL, 5-9
CNCR_MODE_ENB, 8-3, 8-22, 24-10
COMPTIM, 14-9
CONT_CMP, 17-4
CPU_PRI, 8-8
CPU_RST, 6-4, 6-7
CTR_MODE, 16-4
DCTS, 21-6
DDCD, 21-6
DDSR, 21-6
DEVICE_NUM, 9-10
DGP, 12-7
DR, 21-7
ECC_CHK_POS, 10-28
EMSI, 21-9
ENABLE, 4-12, 4-17, 9-10, 9-11
ENB, 19-3, 19-4, 19-6
ENH_MODE_ENB, 14-10
EPS, 21-8
ERR_IN_FIFO, 21-8
EXP_SEL, 5-8, 19-4
EXT_CLK, 17-3
FE, 21-8
FIFO_ENB, 21-9, 21-13
FIRST_DLY, 12-8
FUNCTION_NUM, 9-10
GNT_TO_ID, 8-23
GNT_TO_INT_ENB, 8-19, 8-23
GNT_TO_STA, 8-19
GP_ECHO_ENB, 24-10
GP_RST, 6-4, 6-7, 13-22
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