Index
Élan™SC520 Microcontroller User’s Manual Index-7
F
FE bit field, 21-8
FERRMAP register, 15-5
fields.
See
bit fields.
FIFO_ENB bit field, 21-9, 21-13
FIRST_DLY bit field, 12-8
Flash memory.
See
ROM/Flash controller.
FLASHWR
signal
description, 2-6
usage, 24-6
Floating Point Error Interrupt Clear (FPUERRCLR)
register
function, 7-1, 15-7
usage, 15-12
Floating Point Error Interrupt Mapping (FERRMAP)
register
function, 7-1, 15-5
floating point unit (FPU), 7-3
error handling, 15-12, 15-19
FPUERRCLR register, 15-7
FRAME
signal
description, 2-7
usage, 9-3, 9-9
FUNCTION_NUM bit field, 9-10
G
general-purpose (GP) bus
block diagram (figure), 13-2
bus cycles, 13-16
8-bit access of 16-bit I/O device (figure), 13-19
8-bit access of 8-bit I/O device (figure), 13-16
16-bit access of 16-bit I/O device (figure), 13-17
16-bit access of 8-bit I/O device (figure), 13-17
32-bit access of 16-bit I/O device (figure), 13-18
32-bit access of 8-bit I/O device (figure), 13-18
differentiating byte accesses of 16-bit devices
(table), 13-19
GPIOCS16
and GPMEMCS16 timing, 13-19
GPRDY timing (figure), 13-21
wait states, 13-20
bus sizing, 13-19
dynamic bus sizing override (table), 13-20
chip select qualification, 13-9
configuration, 4-15
configuring external GP bus devices, 3-7, 3-13
multiple devices on one chip select, 3-14
single device performing its own decode, 3-14
single device using one chip select, 3-14
configuring Programmable Address Region x
(PARx) registers, 3-8
data sizing, 13-9
DMA interface, 13-11
echo mode, 13-8, 13-10
echo mode minimum timing (table), 13-9
GP bus reset, 6-7
I/O space, 4-14
I/O-mapped device support, 13-9
initialization, 13-22
interrupts, 13-21
ISA bus compatibility, 13-11
ISA signals and GP bus signals (table), 13-12
latency, 13-21
8/16-bit GP bus width, 13-21
noncacheable GP bus, 13-21
slow GP bus cycles, 13-21
memory space, 4-9
memory-mapped device support, 13-9
operation, 13-6
overview, 13-1
programmable timing, 13-7
GPRDY, 13-8
programmable timing format (figure), 13-8
timing requirements, 13-7
registers, 13-5
serial communications controller interface, 13-14
Am85C30 interface (figure), 13-15
Am85C30 interface timing (figure), 13-16
sharing address and data bus with ROM/
Flash, 13-10
signal descriptions, 2-7, 2-11
Super I/O controller interface, 13-13
Super I/O controller interface (figure), 13-13
Super I/O interface timing (figure), 13-14
system design, 13-1
external data buffer (figure), 13-4
loading, 13-4
shared signals (table), 13-3
voltage translation, 13-4
voltage translation example (figure), 13-5
unaligned accesses, 13-9
usage scenarios, 13-11
general-purpose (GP) timers
block diagram (figure), 17-2
cascaded 32-bit timer, 17-6
clocking considerations, 17-5
external clock sources (table), 17-6
internal clock sources (table), 17-5
configuration, 17-5
GP Timer 0, 17-3
GP Timer 1, 17-3
GP Timer 2, 17-4
initialization, 17-8
interrupts, 17-6
operating modes, 17-4
alternate compare mode, 17-4
continuous mode, 17-4
hardware retrigger mode, 17-4
interrupt on terminal count mode, 17-4
prescaler mode, 17-4
square wave mode, 17-4
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