Index
Élan™SC520 Microcontroller User’s Manual Index-11
H
HBCTL register, 9-7
HBMSTIRQCTL register, 9-7
HBMSTIRQSTA register, 9-7
HBTGTIRQCTL register, 9-7
HBTGTIRQSTA register, 9-7
Header Type (PCIHEADTYPE) register
function, 9-8
HI_PRI_0_SEL bit field, 8-8
HI_PRI_1_SEL bit field, 8-8
Host Bridge Control (HBCTL) register
function, 6-3, 9-7
usage, 6-7, 9-11, 9-19, 9-21, 9-29
Host Bridge Master Interrupt Address (MSTINTADD)
register
function, 9-7
usage, 9-12, 9-27
Host Bridge Master Interrupt Control (HBMSTIRQCTL)
register
function, 9-7
usage, 8-19
Host Bridge Master Interrupt Status (HBMSTIRQSTA)
register
function, 9-7
usage, 9-27
Host Bridge Target Interrupt Control (HBTGTIRQCTL)
register
function, 9-7
usage, 8-19
Host Bridge Target Interrupt Status (HBTGTIRQSTA)
register
function, 9-7
usage, 9-27
HOUR_MODE_SEL bit field, 20-7
I
I/O map.
See
address mapping.
ICE_HRST_DET bit field, 6-8
ICE_ON_RST bit field, 6-5, 6-7, 24-11
ICE_SRST_DET bit field, 6-8
ICEMAP register, 15-5
initialization
See also
system initialization.
address mapping, 4-20
Am5
x
86® CPU, 7-5
clocks, 5-9
general-purpose (GP) bus, 13-22
general-purpose (GP) timers, 17-8
GP-DMA controller, 14-19
JTAG test access port (TAP) controller, 25-20
PCI host bridge, 9-29
power-on reset, 6-9
programmable input/output (PIO), 23-6
programmable interrupt controller (PIC), 15-20
programmable interval timer (PIT), 16-7
read buffer, 11-15
real-time clock (RTC), 20-10
reset types, 6-3
ROM/Flash controller, 12-14
SDRAM controller, 10-29
software timer, 18-3
synchronous serial interface (SSI), 22-8
system arbiter, 8-22
system reset, 6-4
UART serial ports, 21-13
watchdog timer (WDT), 19-6
write buffer, 11-15
Initiator Ready signal.
See
IRDY signal.
INST_TRCE signal
description, 2-13
usage, 26-2
Instruction (IR) register
function, 25-2
usage, 25-3, 25-3, 25-4, 25-15, 25-17, 25-20
instruction set manual, xxiv
Instruction Trace signal.
See
INST_TRCE signal.
INT_ENB bit field, 17-4
INTA
–INTD signals
control, 9-7
description, 2-7, 15-4
usage, 9-2, 15-2, 15-8
Interrupt Control (PICICR) register
function, 15-4
usage, 3-19, 7-6, 15-14, 15-18, 20-10
Interrupt Pin Polarity (INTPINPOL) register
function, 9-7, 15-4
usage, 3-20
Interrupt Request signals.
See
INTA–INTD signals.
interrupts.
See
programmable interrupt controller (PIC).
INTPINPOL register, 15-4
IRDY
signal
description, 2-7
usage, 9-3
IRQ_FLG bit field, 19-4, 19-5
ISA bus compatibility
ISA features not supported, 13-11
ISA signals and GP bus signals (table), 13-12
J
JTAG boundary scan test interface
block diagram (figure), 25-1
Boundary Scan register (figure), 25-1
bus cycles, 25-18
data scan (figure), 25-19
instruction scan (figure), 25-20
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