AMD Elan SC520 - Page 426

Index
Index-12 Élan™SC520 Microcontroller User’s Manual
clocking considerations, 25-20
configuration information, 25-4
bypass path, 25-5
instruction path, 25-4
main data scan path, 25-5
Device Identification register (figure), 25-14
initialization, 25-20
instruction register, 25-3
BYPASS instruction, 25-4
EXTEST instruction, 25-3
HIGHZ instruction, 25-4
IDCODE instruction, 25-4
SAMPLE/PRELOAD instruction, 25-3
main data scan path (table), 25-5
operation, 25-2
overview, 25-1
registers, 25-2
Serial Debug Port Data register (figure), 25-13
signal descriptions, 2-12
TAP controller state diagram (figure), 25-15
TAP instruction set (table), 25-3
test access port (TAP) controller, 25-14
capture-DR state, 25-16
capture-IR state, 25-17
exit1-DR state, 25-16
exit1-IR state, 25-18
exit2-DR state, 25-17
exit2-IR state, 25-18
pause-DR state, 25-16
pause-IR state, 25-18
run-test-idle state, 25-15
select-DR-scan state, 25-16
select-IR-scan state, 25-17
shift-DR state, 25-16
shift-IR state, 25-17
test-logic-reset state, 25-15
update-DR state, 25-17
update-IR state, 25-18
JTAG_TCK signal
description, 2-12
usage, 25-2, 25-3, 26-2
JTAG_TDI signal
description, 2-12
usage, 25-2, 25-4, 26-2
JTAG_TDO signal
description, 2-12
usage, 25-2, 25-3, 25-4, 26-2
JTAG_TMS signal
usage, 2-12, 25-14, 26-2
JTAG_TRST signal
description, 2-12
usage, 25-14
L
LF_PLL1 signal
description, 2-10
usage, 5-2
logic diagram
default pin function, 2-3
interface, 2-2
LOOP bit field, 21-13
Loop Filter Interface signal.
See LF_PLL1 signal.
LTIM bit field, 3-19
M
M_AD_IRQ_ID bit field, 9-27
M_CMD_IRQ_ID bit field, 9-27
M_GINT_MODE bit field, 15-18
M_RETRY_TO bit field, 9-12, 9-28
M_WPOST_ENB bit field, 9-11
MA12–MA0 signals
control, 10-10, 10-19
description, 2-5
usage, 10-31, 24-4, 24-7, 24-9
Master DMA Channel 4–7 Control (MSTDMACTL)
register
function, 14-7
Master DMA Channel 4–7 Mask (MSTDMAMSK)
register
function, 14-7
Master DMA Channel 4–7 Mode (MSTDMAMODE)
register
function, 14-7
usage, 14-11, 14-14, 14-19
Master DMA Channel 4–7 Status (MSTDMASTA)
register
function, 14-7
Master DMA Channel x Memory Address
(GPDMAxMAR) register
function, 14-7
usage, 14-11, 14-12, 14-18
Master DMA Channel x Page (GPDMAxPG) register
function, 14-7
usage, 14-11, 14-12
Master DMA Channel x Transfer Count (GPDMAxTC)
register
function, 14-7
usage, 14-9, 14-18
Master DMA Clear Byte Pointer (MSTDMACBP)
register
function, 14-7
Master DMA Controller Reset (MSTDMARST) register
function, 14-8
usage, 14-19