Index
Élan™SC520 Microcontroller User’s Manual Index-27
operation, 8-3
PCI bus arbiter, 8-7
arbitration protocol, 8-8
bus parking, 8-10
external PCI master queues (figure), 8-9
host bridge master queue (figure), 8-9
rearbitration, 8-10
registers, 8-2
software considerations, 8-19
write posting, 8-19
System Board Information (SYSINFO) register
function, 6-3
usage, 19-6
System Control Port A (SYSCTLA) register
function, 6-3, 7-1
usage, 6-7, 6-8
System Control Port B (SYSCTLB) register
function, 16-3
usage, 16-4
System Error signal.
See
SERR signal.
system initialization
BIOS initialization sequence, 3-3
configuration register access, 4-19
CPU core identification, 3-7
CPU speed, 3-7
disabling internal peripherals, 3-21
external GP bus devices, 3-7
multiple devices on one chip select, 3-14
single device performing its own decode, 3-14
single device using one chip select, 3-14
external ROM devices
boot device mapping for BIOS shadowing, 3-17
two Flash banks for XIP operating system, 3-17
interrupt mapping, 3-19
edge-sensitive or level-triggered interrupts, 3-19
interrupt polarity, 3-20
memory-mapped configuration region (MMCR), 3-3
native embedded initialization sequence, 3-1
PCI bus devices
network adapter, 3-16
VGA controller on PCI bus, 3-15
PCI host bridge and arbitration, 3-20
pin multiplexing, 3-8
Programmable Address Region x (PARx) regions
specifying pages and regions, 3-9
Programmable Address Region x (PARx)
registers, 3-8
address region attributes, 3-12
cacheability control, 3-12
code execution control, 3-12
external GP bus devices, 3-13
external ROM devices, 3-17
format (figure), 3-10
PAR register priority, 3-13
PCI bus devices, 3-15
performance considerations of attributes, 3-12
SDRAM regions, 3-18
worksheet (figure), 3-11
write-protection, 3-12
programmable I/O pins, 3-20
reset event, 3-4
reset vector and reset segment, 3-5
initial near jump example (figure), 3-6
SDRAM regions
configuring DMA buffers, 3-18
write-protected code segments, 3-18
system reset, 6-6
system test and debugging
cache mode control, 24-10
CPU clock speed control, 24-10
disabling write buffer and read buffer, 24-10
ECC check code override, 24-11
echoing integrated peripheral accesses, 24-10
execution control violation notification, 24-11
forcing software interrupts, 24-11
initialization, 24-12
interrupt masking, 24-11
latency, 24-11
nonconcurrent arbitration mode, 24-10
operation, 24-3
overview, 24-1
registers, 24-2
reset source identification, 24-11
software considerations, 24-11
system design, 24-1
loading, 24-2
logic analyzer use, 24-2
shared signals (table), 24-2
system test mode, 24-3
pin functions, 24-3
SDRAM read cycle (figure), 24-5
SDRAM write cycle (figure), 24-4
tracing transactions on GP bus, 24-6
tracing transactions on ROM interface, 24-5
write buffer test mode, 24-7
SDRAM read cycle (figure), 24-8
SDRAM write cycle (figure), 24-8
WBMSTR2–WBMSTR0 during SDRAM read
cycles (table), 24-9
WBMSTR2–WBMSTR0 during write buffer write
cycles (table), 24-8
write protection violation notification, 24-11
SZ_ST_ADR bit field, 3-9, 3-10, 4-5
T
T_DLYTR_ENB bit field, 9-19
T_IRQ_ID bit field, 9-27
T_PURGE_RD_ENB bit field, 9-21
T7–T3 bit field, 15-18
TARGET bit field, 3-10, 4-5, 4-8, 4-15, 4-18, 9-18
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