Index
Index-28 Élan™SC520 Microcontroller User’s Manual
Target Ready signal.
See
TRDY signal.
TC_INT bit field, 22-7
TC_INT_ENB bit field, 22-7
technical support, iii
TEMT bit field, 21-7
TERI bit field, 21-6
test access port (TAP) controller.
See
JTAG boundary
scan test interface.
Test Clock Output signal.
See
CLKTEST signal.
Test Data Input signal.
See
JTAG_TDI signal.
Test Data Output signal.
See
JTAG_TDO signal.
Test Mode Select signal.
See
JTAG_TMS signal.
testing.
See
JTAG boundary scan test interface.
See
also
system test and debugging.
See also
AMDebug™ technology.
TF_CLR bit field, 21-10
third-party support products, iii
THRE bit field, 21-6
Timer Clock Input signal.
See
CLKTIMER signal.
Timer Input 0 and 1 signals.
See
TMRIN1–TMRIN0
signals.
Timer Output 0 and 1 signals.
See
TMROUT1–
TMROUT0 signals.
TMRIN1–TIMIN0 signals
control, 13-3, 13-6, 17-1
description, 2-10
usage, 17-3, 17-4, 17-6
TMROUT1–TMROUT0 signals
control, 13-3, 13-6, 17-1
description, 2-10
usage, 14-3, 17-5
TRDY
signal
description, 2-7
usage, 9-3, 9-20, 9-21
TRIG/TRACE signal
control, 25-4
description, 2-12
Trigger/Trace signal.
See
TRIG/TRACE signal.
TRNMOD bit field, 14-11, 14-19
U
UART serial ports
baud rates, divisors, and clock source (table), 21-9
block diagram (figure), 21-2
clocking considerations, 21-10
configuration, 21-9
baud rate, 21-9
hardware flow control, 21-9
operating modes, 21-9
data reception, 21-7
data transmission, 21-6
disabling, 3-21
DMA interface, 21-10
receive DMA, 21-10
transmit DMA, 21-10
UART as GP-DMA initiator, 14-9
error handling, 21-8
break indication, 21-8
error reporting, 21-8
framing error, 21-8
parity error, 21-8
frame configuration (figure), 21-5
frame transmission (figure), 21-5
GP-DMA channel mapping (table), 14-10
initialization, 21-13
interrupts, 21-10
DMA interrupts, 21-12
interrupt disable, 21-13
interrupt priority (table), 21-12
interrupt programming summary (table), 21-11
serial port interrupts, 21-12
operation, 21-5
overview, 21-1
registers, 21-3
signal descriptions, 2-9
system design, 21-2
connection of DTE to DTE (table), 21-3
shared signals (table), 21-2
UART x Baud Clock Divisor Latch LSB (UARTxBCDL)
register
function, 21-4
usage, 21-9
UART x Baud Clock Divisor Latch MSB (UARTxBCDH)
register
function, 21-4
usage, 21-9
UART x FIFO Control (UARTxFCR) register
function, 21-4
usage, 21-3, 21-7, 21-9, 21-10, 21-13
UART x FIFO Control Shadow (UARTxFCRSHAD)
register
function, 21-3
usage, 21-13
UART x General Control (UARTxCTL) register
function, 5-6, 21-3
usage, 5-8, 21-9, 21-10, 21-11, 21-12
UART x General Status (UARTxSTA) register
function, 21-3
usage, 21-11, 21-12
UART x Interrupt Enable (UARTxINTENB) register
function, 21-4
usage, 21-9, 21-11
UART x Interrupt ID (UARTxINTID) register
function, 21-4
usage, 21-11, 21-12
UART x Interrupt Mapping (UARTxMAP) register
function, 15-5, 21-3, 21-11
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