AMD Elan SC520 - Page 443

Index
Élan™SC520 Microcontroller User’s Manual Index-29
UART x Line Control (UARTxLCR) register
function, 21-4
usage, 21-5, 21-8
UART x Line Status (UARTxLSR) register
function, 21-4
usage, 21-6, 21-7, 21-8, 21-10, 21-11
UART x Modem Control (UARTxMCR) register
function, 21-4
usage, 21-6, 21-11, 21-13
UART x Modem Status (UARTxMSR) register
function, 21-4
usage, 21-6, 21-11
UART x Receive Buffer (UARTxRBR) register
function, 21-4
usage, 21-7, 21-8, 21-10
UART x Scratch Pad (UARTxSCRATCH) register
function, 21-4
UART x Transmit Holding (UARTxTHR) register
function, 21-4
usage, 21-5, 21-6, 21-7, 21-10
UART1_DIS bit field, 3-21
UART2_DIS bit field, 3-21
UARTxBCDH register, 21-4
UARTxBCDL register, 21-4
UARTxCTL register, 21-3
UARTxFCR register, 21-4
UARTxFCRSHAD register, 21-3
UARTxINTENB register, 21-4
UARTxINTID register, 21-4
UARTxLCR register, 21-4
UARTxLSR register, 21-4
UARTxMAP register, 15-5
UARTxMCR register, 21-4
UARTxMSR register, 21-4
UARTxRBR register, 21-4
UARTxSCRATCH register, 21-4
UARTxSTA register, 21-3
UARTxTHR register, 21-4
UIP bit field, 20-7
universal asynchronous receiver/transmitter (UART).
See UART serial ports.
V
VCC_ANLG signal
description, 2-14
usage, 5-3, 20-4
VCC_CORE signal
description, 2-14
VCC_I/O signal
description, 2-14
VCC_RTC signal
usage, 2-10, 2-14, 6-9, 20-3, 20-4, 20-11
W
watchdog timer (WDT)
AMDebug™ technology interface, 19-5
block diagram (figure), 19-2
configuration, 19-3
interrupt request generation, 19-4
keyed sequences, 19-3
system reset generation, 19-4
time-out duration, 19-4
initialization, 19-6
interrupts, 19-5
operation, 19-3
overview, 19-1
registers, 19-2
software considerations, 19-5
time-out duration (table), 19-4
Watchdog Timer Control (WDTMRCTL) register
function, 6-3, 19-2
usage, 5-8, 19-3, 19-4, 19-5, 19-6
Watchdog Timer Count High (WDTMRCNTH) register
function, 19-3
usage, 19-6
Watchdog Timer Count Low (WDTMRCNTL) register
function, 19-2
usage, 19-6
Watchdog Timer Interrupt Mapping (WDTMAP) register
function, 15-5, 19-3
WB_ENB bit field, 24-10
WB_FLUSH bit field, 11-5, 11-13
WB_TST_ENB bit field, 10-19, 24-2, 24-3, 24-7
WB_WM bit field, 11-9
WBMSTR2–WBMSTR0 signals
control, 24-2
description, 2-13
usage, 10-19, 11-4, 24-1, 24-7, 24-8, 24-12
WDT.
See watchdog timer (WDT).
WDT_RST_DET bit field, 6-8
WDTMAP register, 15-5
WDTMRCNTH register, 19-3, 19-6
WDTMRCNTL register, 19-2
WDTMRCTL register, 19-2
web site, iii
WIDTH bit field, 12-7
WPVMAP register, 15-5
WPVSTA register, 4-2
write buffer and read buffer
block diagram (figure), 11-2
data coherency, 11-13
disabling during SDRAM sizing or test, 11-13