Index
Index-26 Élan™SC520 Microcontroller User’s Manual
SSIRCV register, 22-2
SSISTA register, 22-2
SSIXMIT register, 22-2
Status/Command (PCISTACMD) register
function, 9-8
usage, 9-10, 9-18, 9-27
STOP
signal
description, 2-7
usage, 9-3
Stop/Transmit signal.
See
STOP/TX signal.
STOP/TX signal
control, 25-4
description, 2-12
SUB_DLY bit field, 12-8
SWEA
–SWEB signals
control, 10-10, 10-19, 23-4
description, 2-5
usage, 10-5
SWINT16_1 register, 15-4
SWINT22_17 register, 15-4
SWT.
See
software timer.
SWTMRCFG register, 18-2
SWTMRMICRO register, 18-2
SWTMRMILLI register, 18-2
SxPICICW1 register, 15-6
SxPICICW2 register, 15-6
SxPICICW3 register, 15-7
SxPICICW4 register, 15-7
SxPICINTMSK register, 15-7
SxPICIR register, 15-6
SxPICISR register, 15-6
SxPICOCW2 register, 15-6
SxPICOCW3 register, 15-6
synchronous DRAM.
See
SDRAM controller.
synchronous serial interface (SSI)
block diagram (figure), 22-2
bus cycles, 22-5
4-bit read cycle, 22-6
burst, 16-bit, and 32-bit cycles, 22-7
clock phase and clock idle state (figure), 22-6
full-duplex, back-to-back transactions
(figure), 22-7
full-duplex, non-inverted phase, non-inverted
clock (figure), 22-6
half-duplex, non-inverted phase and clock
modes (figure), 22-4
simultaneous transmit and receive (figure), 22-4
TC_INT and BSY_STA timing (figure), 22-8
clocking considerations, 22-7
configuration, 22-5
bit order, 22-5
clock idle state, 22-5
clock phase, 22-5
initialization, 22-8
interrupts, 22-7
operation, 22-3
overview, 22-1
registers, 22-2
signal descriptions, 2-9
software considerations, 22-8
system design, 22-1
four-pin interface (figure), 22-4
three-pin interface (figure), 22-4
SYS_RST bit field, 6-4, 6-5
SYSARBCTL register, 8-2
SYSARBMENB register, 8-2
SYSCTLA register, 6-3
SYSCTLB register, 16-3
SYSINFO register, 6-3
System Arbiter Control (SYSARBCTL) register
function, 8-2, 24-2
usage, 8-3, 8-10, 8-19, 8-22, 24-10
System Arbiter Master Enable (SYSARBMENB)
register
function, 8-2
usage, 8-19, 8-23
system arbitration
arbitration mode changes, 8-19
block diagram (figure), 8-2
broken transactions, 8-19
bus cycles, 8-11
CPU bus arbitration (figure), 8-11
CPU bus cache write-back (figure), 8-12
CPU-to-PCI cycle (figure), 8-14
nonconcurrent mode arbitration (figure), 8-18
PCI bus arbitration (figure), 8-15
PCI bus arbitration parking (figure), 8-16
CPU bus arbiter, 8-5
accessing the PCI host bridge target, 8-6
arbitration protocol, 8-5
cache snooping, 8-6
clock speed changes, 8-7
GP-DMA arbitration, 8-7
rotating priority queue (figure), 8-6
skipped master example (figure), 8-5
initialization, 8-22
interrupts, 8-19
latency, 8-20
concurrent arbitration mode, 8-22
concurrent arbitration mode bus parking, 8-22
CPU, 8-21
high-priority queue, 8-21
low-priority queue, 8-21
nonconcurrent arbitration mode, 8-21
simple rotating priority, 8-20
simple rotating priority queue (figure), 8-20
operating modes, 8-3
concurrent arbitration mode, 8-4
nonconcurrent arbitration mode, 8-3
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