EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 117
Universal Serial Bus (USB)
* and then DP is pulled down. This seems to work without the VBUS. */
/* Enable CHG_VBUS. */
UIB->otg_ctrl |= CY_U3P_UIB_CHG_VBUS;
CyU3PThreadSleep (10);
/* Pullup DP */
regVal = UIB->otg_ctrl & (CY_U3P_UIB_OTG_ENABLE | CY_U3P_UIB_CHG_VBUS);
UIB->otg_ctrl = (regVal | CY_U3P_UIB_DEV_ENABLE | CY_U3P_UIB_DP_PU_EN);
CyU3PThreadSleep (10);
/* Pull down DP */
UIB->otg_ctrl = (regVal | CY_U3P_UIB_HOST_ENABLE | CY_U3P_UIB_DP_PD_EN);
CyU3PThreadSleep (10);
/* Set the PHY to be disconnected. */
UIB->otg_ctrl = regVal;
/* Disable CHG_VBUS. */
UIB->otg_ctrl &= ~CY_U3P_UIB_CHG_VBUS;
CyU3PThreadSleep (10);
return CY_U3P_SUCCESS;
}
The following code example implements the function that accepts the SRP request from the A-device.
static void
CyU3POtgSetupPhy (void)
{
if (CyU3POtgIsHostMode ())
{
/* Enable and set the EPM clock to bus clock (100MHz). */
GCTL->uib_core_clk = (CY_U3P_GCTL_UIBCLK_CLK_EN | CY_U3P_GCTL_UIB_CORE_CLK_DEFAULT);
/* Enable host mode. */
UIB->otg_ctrl &= CY_U3P_UIB_OTG_ENABLE;
UIB->otg_ctrl |= CY_U3P_UIB_HOST_ENABLE;
/* Reset and enable the PHY. */
UIB->phy_clk_and_test = (CY_U3P_UIB_DATABUS16_8 | CY_U3P_UIB_VLOAD |
CY_U3P_UIB_RESET | CY_U3P_UIB_EN_SWITCH);
CyU3PBusyWait (10);
UIB->phy_clk_and_test &= ~CY_U3P_UIB_RESET;
UIB->phy_clk_and_test |= CY_U3P_UIB_SUSPEND_N;
CyU3PBusyWait (100);
/* Switch EPM clock to 120MHz. */
GCTL->uib_core_clk &= ~CY_U3P_GCTL_UIBCLK_EPMCLK_SRC_MASK;
/* Make sure EHCI is the owner of the port. */
UIB->ehci_configflag = CY_U3P_UIB_CF;
CyU3PBusyWait (10);
}
if (CyU3POtgIsDeviceMode ())
{
UIB->otg_ctrl &= CY_U3P_UIB_OTG_ENABLE;
UIB->otg_ctrl |= CY_U3P_UIB_DEV_ENABLE;
/* Enable and set the EPM clock to bus clock (100MHz). */
GCTL->uib_core_clk = (CY_U3P_GCTL_UIBCLK_CLK_EN |
CY_U3P_GCTL_UIB_CORE_CLK_DEFAULT);