EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 140
General Programmable Interface II (GPIF II)
When you select Master or Slave, the Action List (right panel) automatically updates to show the available choices for the
selection.
3. Does this interface use a clock?
A GPIF II-based interface can be synchronous or asynchronous in nature. In the case of a synchronous project, the GPIF
II state machine operates using the same clock that is used on the interface. A given GPIF II configuration is asynchro-
nous or synchronous; it is not possible to have both coexisting in a given configuration.
An example of an asynchronous interface is a static RAM that has an address and data bus, read and write strobes, but
no clock. A read operation, for example, occurs by asserting the address, and then asserting chip enable and read
strobes. The data comes out a propagation time after the read strobe, with no reference to a clock.
4. Do you want FX3 GPIF II to drive the interface clock?
If yes, then select Internal; otherwise, select External. This section is dimmed out if you do not select Synchronous in
question 3.
This interface clock can be generated and driven out by the FX3 device or provided as input to the FX3 device. The max-
imum frequency supported for the GPIF II interface clock is 100 MHz.
5. When do you want GPIF II to sample interface signals? On the positive edge or the negative edge?
This section is dimmed out if you do not select Synchronous in question 3.
6. Endian-ness of your device: Little endian or big endian?.
"Endian-ness" refers to byte ordering in multibyte integers-most significant (big) or least significant (little) byte first.
7. Data bus width of the external device connected to FX3: 8-bit, 16-bit, 24-bit or 32-bit?
A GPIF II interface offers a maximum of 32 bidirectional data lines, which can be split into, or time multiplexed with,
address lines. In multiplexed operation, the address bus has the same width as the data bus. One of the control pins can
be used to implement the ADV or ALE signal required to control the functionality of the address/data multiplexed bus. If
the address bus is not time multiplexed with the data bus, the number of address lines available will depend on the width
of the data bus.
8. Does the external device require address lines?
This would be true if the device needs to select between FX3 resources, such as threads, sockets (configured as Slave in
GPIF II) or to select the particular memory region on the external device (configured as Master in GPIF II).
9. Do you want to enable special functions?
Some of the general-purpose I/O signals of FX3 can be associated with special functions that are commonly used in stan-
dard protocols. These special functions are only available on specific pins, and control signals that use them cannot be
moved to other pins. The enables are:
OE: Output Enable. Provides direct control of output drivers. The OE signal directly controls whether the data bus is
driven or tristated by the FX3, so that the latencies associated with doing this through the GPIF II state machine are
removed.
WE: Write Enable. Provides direct control to disable output drivers on the data bus. The data bus will not be driven by FX3
if the WE special function is selected and the WE input is asserted.
DLE: Data Latch Enable. Enables the input stage on the FX3 data bus to latch data. This special function is normally com-
bined with the WE function.
ALE: Address Latch Enable. Enables the input address stage on the FX3 to latch address values.
DRQ: DMA Request. Provides a DMA request output that is controlled through the GPIF II state machine and that
responds to the DACK input signal.
DACK: DMA Acknowledge. This is not a separate special function, but an input that is used to control the behavior of the
DRQ signal.
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