EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 278
GCTL_WATCHDOG_CS
0xE0050014
10.5.5 GCTL_WATCHDOG_CS (continued)
9:8 MODE1[1:0] Counter mode:
0 Free-running mode, counter wraps around after 32 bits.
1 Interrupt mode, interrupt when COUNTER & ~((~0)<<BITS) = 0.
2 Reset mode, full chip RESET when COUNTER & ~((~0)<<BITS) = 0.
3 Disable - counter does not run
7:3 BITS0[4:0] Number of least significant bits to be used when checking for counter limit (useful only for
MODE = 1, 2)
2 INTR0 Interrupt signal (Mode 1 only). This bit indicates when the WDOG timer has issued an interrupt to the
CPU while the system is powered up. Refer to the GCTL_WAKEUP_EVENT register when the
WDOG timer is used to wake up the system from a power-down state.
1:0 MODE0 Counter mode:
0 Free-running mode, counter wraps around after 32 bits.
1 Interrupt mode, interrupt when COUNTER & ~((~0)<<BITS) = 0.
2 Reset mode, full chip RESET when COUNTER & ~((~0)<<BITS) = 0.
3 Disable - counter does not run