EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 645
SDMMC_MODE_CFG
0xFC
10.26.17 SDMMC_MODE_CFG (Continued)
19 RD_END_STOP_CLK_EN 0: Do not Stop SD/MMC interface clock at the end of a read data transfer.
1: Stop interface clock at the end of read data transfer.
18 CARD_DETECT_POLARITY0: CardDetect GPIO is active LOW.
1: CardDetect GPIO is active HIGH.
This value is used by hardware to reflect the S0S1_INS status in the SDMMC_STATUS.card_detect
register bit.
16 WR_STOP_CLK_EN This enables SIB to perform detection of underflow and stop the clock to the SD/SDIO/MMC card
during data transfer.
1: Enable stop clock.
0: Disable stop clock.
15 RD_STOP_CLK_EN This enables SIB to perform detection of overflow and stop the clock to the SD/SDIO/MMC card
during data transfer:
1: Enable stop clock.
0: Disable stop clock.
This bit should always be set during read operations to prevent loss of data.
14 EN_CMD_COMP Enable command completion feature for CE-ATA interface.
0: Don't detect command completion event.
1: Detect command completion event.
When EN_CMD_COMP is enabled, RD_END_STOP_CLK should not be enabled because card
requires a clock edge to provide command completion signal.
13:12 DATABUSWIDTH SIB data bus width:
00: 1-bit
01: 4-bit
10: 8-bit
11: Reserved
11:10 MODE SIB interface mode:
00: Reserved
01: MMC (or CE-ATA)
10: SD
11: Reserved
9:6 SIGNALING SD/MMC data signaling parameters:
0000: DS - Default-Speed (0 - 20 MHz for MMC; 0 - 25 MHz for SD)
0001: HS - High-Speed (0 - 52 MHz for MMC; 0 - 50 MHz for SD)
0010: SDR12: SD SDR 25 MHz @1.8 V
0011: SDR25: SD SDR 50 MHz @1.8 V
0100: SDR50_FD: SD SDR 100 MHz @ 1.8 V
0101 - 0111: Reserved
1000: DDR52_V33_MMC
1001: DDR52_V18_MMC
1010: Reserved
1011: DDR50_V18_SD: As defined in SD3.0
1100 - 1111: Reserved
5 DLL_BYPASS_EN Setting this bit causes the SIB internal clock to be driven out on the pad bypassing the DLL. It is rec-
ommended that this bit should always be set to 1.
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