EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 650
SDMMC_STATUS
0xFC
10.26.20 SDMMC_STATUS
18 RD_END_DATA_ERROR This error is flagged when command, response or NRC counting is in progress when the last byte of
the last block of read-data is read while RD_END_CLK_STOP is enabled. This condition causes data
from card to be read out of card and dropped. FW should re-issue read command to card to restart
read command.
This bit is cleared when SDMMC_CS.RDDCARD is set by FW.
17 DAT0_STAT Reflects the current status of the SD_DAT[0] pin.
16 DLL_LOCKED Reflects the current lock status of the SIB DLL.
1: DLL is locked.
0: DLL Is not locked.
15 DLL_LOST_LOCK Reflects the current lock status of the SIB DLL.
1: DLL is not locked.
0: DLL Is locked.
14 BOOT_ACK HW sets this bit to ‘1’ when a MMC boot acknowledgement is detected.
This bit is cleared when FW clears the SDMMC_MODE_CFG.EXP_BOOT_ACK bit.
13 CMD_COMP HW sets this bit to ‘1’ when Command Completion signaling from a CE-ATA peripheral is detected.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.SNDCMD again.
12 FIFO_U_DET HW sets this bit to ‘1’ if a FIFO underflow is detected during a write operation.
The bit is cleared when FW writes ‘1’ to SDMMC_CS.WRDCARD again.
11 FIFO_O_DET HW sets this bit to ‘1’ if a FIFO overflow is detected during a read operation.
The bit is cleared when FW writes ‘1’ to SDMMC_CS.RDDCARD again.
10 DAT3_STAT Reflects the state of the SD_DAT[3] pin.
9 CARD_DETECT Reflects the state of the S0S1_INS pin.
0: No card inserted (GPIO is inactive).
1: Card is inserted (GPIO is active).
8SDIO_INTR HW sets this bit to ‘1’ when it detects an SDIO interrupt condition. This bit will represent the latest
result of the interrupt sampling.
7 CRC16_ERROR HW sets this bit to ‘1’ if a CRC error is detected during a read or write data operation.
This bit is cleared when FW writes ‘1’ to SDMMC_CS.RDDCARD or WRDCARD again.
6 RD_DATA_TIMEOUT HW sets this bit to ‘1’ if a read data operation times out.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.RDDCARD again.
5 BLOCKS_RECEIVED HW sets this bit to ‘1’ when the read of NOBD blocks of data is completed.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.RDDCARD again.
4BLOCK_COMP HW sets this bit to ‘1’ when the write of NOBD blocks of data is completed.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.WRDCARD again.
3 CRC7_ERROR HW sets this bit to ‘1’ if a CRC error is detected in the response received.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.SNDCMD again.
2 RESPTIMEOUT HW sets this bit to ‘1’ if no response was received within the timeout period.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.SNDCMD again.
1 RCVDRES HW sets this bit to ‘1’ when the command response is received.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.SNDCMD again.
0 CMDSENT HW sets this bit to ‘1’ when a command is sent.
This bit is cleared when the FW writes ‘1’ to SDMMC_CS.SNDCMD a
gain.
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