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RM0090 Rev 18 1727/1749

RM0090 Revision history

1743

03-Feb-2014 6

Added note related to over-drive mode unavailable in 1.8 to 2.1 V V

DD ran

in Section 3.5.1: Relation between CPU clock frequency and Flash

memory read time.

Updated maximum CPU frequency in Section 3.5.2: Adaptive real-time

memory accelerator (ART Accelerator™).

PWR:

Updated Run mode/ over-drive mode in Section 5.1.4: Voltage regulator for

STM32F42xxx and STM32F43xxx.

RCC for STM32F42/43xx:

Changed APB1/2 and AHB maximum frequencies.xw

GPIOs:

Updated Figure 27: Selecting an alternate function on STM32F42xxx and

STM32F43xxx.

DMA:

Updated Section 10.3.7: Pointer incrementation and Section 10.3.11: Single and

burst transfers..

INTERRUPTS AND EVENTS:

Updated Table 62: Vector table for STM32F42xxx and STM32F43xxx.

ADC:

Updated Section 13.3.10: Discontinuous mode/Section : Regular group.

DCMI:

Updated Section 15.5.2: DCMI physical interface.

LTDC:

Updated resolution in note below Figure 82: LCD-TFT Synchronous timings.

TIM1 and 8:

Added note related to IC1F in Section 17.4.7: TIM1 and TIM8 capture/compare

mode register 1 (TIMx_CCMR1).

TIM2 to 5:

Updated note related to IC1F in Section 18.4.7: TIMx capture/compare mode

Table 315. Document revision history (continued)

Date Version Changes

ST STM32F405 User Manual

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