ST STM32F405 User Manual

Revision history RM0090
1728/1749 RM0090 Rev 18
03-Feb-2014
6
(continued)
TIM9 to 14:
Updated note related to IC1F in Section 19.5.5: TIM10/11/13/14 capture/compare
mode register 1 (TIMx_CCMR1).
RTC:
Updated Section 26.3.11: RTC smooth digital calibration.
Changed ALRBIE to ALRBE (bit 9) in Section 26.6.3: RTC control register
(RTC_CR).
I2C:
Introduced Sm (standard mode) and Fm (fast mode) acronyms.
FSMC:
Updated BUSTURN definition in Table 245: FSMC_BTRx bit fields.
FMC:
Added Mobile LPSDR SDRAM.
Updated Section : SDRAM initialization and Section : SDRAM controller read cycle
and Figure 476: NAND Flash/PC Card controller waveforms for common memory
access.
Updated Section : SRAM/NOR-Flash chip-select control registers 1..4
(FMC_BCR1..4), Section : SRAM/NOR-Flash chip-select timing registers 1..4
(FMC_BTR1..4), Section : SRAM/NOR-Flash write timing registers 1..4
(FMC_BWTR1..4), Section : SDRAM Timing registers 1,2 (FMC_SDTR1,2) and
Section : SDRAM Refresh Timer register (FMC_SDRTR).
Removed mention “default valeur after reset” in Section : Common memory space
timing register 2..4 (FMC_PMEM2..4), Section : Attribute memory space timing
registers 2..4 (FMC_PATT2..4), and Section : I/O space timing register 4
(FMC_PIO4).
Updated BUSTURN definition in Table 288: FMC_BTRx bit fields.
Updated REV_ID bits in Section 38.6.1: MCU device ID code..
Table 315. Document revision history (continued)
Date Version Changes

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English