Revision history RM0090
1734/1749 RM0090 Rev 18
16-Mar-2015
9
(continued)
I2C2:
Updated FREQ[5:0] description in Section 27.6.2: I
2
C Control register 2 (I2C_CR2).
USART:
Removed note related to RXNEIE in Section : Reception using DMA
FSMC:
Updated Figure 474: Synchronous multiplexed read mode waveforms - NOR,
PSRAM (CRAM).
USB OTG FS
Updated Table 203: TRDT values
FMC
Updated FMC_NL in Figure 456: FMC block diagram.
Updated ‘Memory wait’ and ‘Memory data bus high-z’ parameters in Table 289:
Programmable NAND Flash/PC Card access parameters.
Updated Section : Common memory space timing register 2..4 (FMC_PMEM2..4).
Updated Figure 476: NAND Flash/PC Card controller waveforms for common
memory access.
DEBUG:
Updated REV_ID[15:0) and JTAG ID code in Section 38.6.1: MCU device ID code
and Section 38.6.2: Boundary scan TAP, respectively
Table 315. Document revision history (continued)
Date Version Changes
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