Agilent Technologies E5071C

E5071C
1128
Bit
Position
Name Description
0
Trace 15, 16 Limit Test
summary (questionable
limit channel {1-16} extra
status register summary)
Set to "1" while one of the
enabled bits in the
questionable limit channel
{1-16} extra status event
register is set to "1."
1 Trace 1 Limit Test Fail
Set to "0" when a
measurement cycle begins;
set to "1" when the
measurement cycle finishes
and returns "fail" as the limit
test result for trace 1.
2 Trace 2 Limit Test Fail
Set to "0" when a
measurement cycle begins;
set to "1" when the
measurement cycle finishes
and returns "fail" as the limit
test result for trace 2.
3 Trace 3 Limit Test Fail
Set to "0" when a
measurement cycle begins;
set to "1" when the
measurement cycle finishes
and returns "fail" as the limit
test result for trace 3.
4 Trace 4 Limit Test Fail
Set to "0" when a
measurement cycle begins;
set to "1" when the
measurement cycle finishes
and returns "fail" as the limit
test result for trace 4.
5 Trace 5 Limit Test Fail
Set to "0" when a
measurement cycle begins;
set to "1" when the
measurement cycle finishes
and returns "fail" as the limit
test result for trace 5.