Agilent Technologies E5071C

E5071C
1130
measurement cycle finishes
and returns "fail" as the limit
test result for trace 12.
13 Trace 13 Limit Test Fail
Set to "0" when a
measurement cycle begins;
set to "1" when the
measurement cycle finishes
and returns "fail" as the limit
test result for trace 13.
14 Trace 14 Limit Test Fail
Set to "0" when a
measurement cycle begins;
set to "1" when the
measurement cycle finishes
and returns "fail" as the limit
test result for trace 14.
15 Not used Always 0
Issuing the *CLS command will clear all the bits in the questionable limit
channel {1-16} status event register.
Status Bit Definitions of the Questionable Limit Channel {1-16}
Extra Status Condition Register
Bit
Position
Name Description
0 Not used Always 0
1
Trace 15
Limit Test
Fail
Set to "0" when a measurement cycle
begins;
set to "1" when the measurement cycle
finishes and returns "fail" as the limit test
result for trace 15.
2
Trace 16
Limit Test
Fail
Set to "0" when a measurement cycle
begins;
set to "1" when the measurement cycle
finishes and returns "fail" as the limit test
result for trace 16.