Agilent Technologies E5071C - Page 919

E5071C
1146
1
Channel 1 Ripple Test Fail
(questionable ripple limit
channel 1 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable ripple limit
channel 1 status event
register is set to "1."
2
Channel 2 Ripple Test Fail
(questionable ripple limit
channel 2 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable ripple limit
channel 2 status event
register is set to "1."
3
Channel 3 Ripple Test Fail
(questionable ripple limit
channel 3 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable ripple limit
channel 3 status event
register is set to "1."
4
Channel 4 Ripple Test Fail
(questionable ripple limit
channel 4 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable ripple limit
channel 4 status event
register is set to "1."
5
Channel 5 Ripple Test Fail
(questionable ripple limit
channel 5 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable ripple limit
channel 5 status event
register is set to "1."
6
Channel 6 Ripple Test Fail
(questionable ripple limit
channel 6 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable ripple limit
channel 6 status event
register is set to "1."
7
Channel 7 Ripple Test Fail
(questionable ripple limit
channel 7 status register
summary)
Set to "1" while one of the
enabled bits in the
questionable ripple limit
channel 7 status event
register is set to "1."
8
Channel 8 Ripple Test Fail
(questionable ripple limit
channel 8 status register
Set to "1" while one of the
enabled bits in the
questionable ripple limit