AMD Elan SC520 - Page 423

Index
Élan™SC520 Microcontroller User’s Manual Index-9
GPA25–GPA0 signals
description, 2-6, 2-7
usage, 2-8, 13-1, 13-4, 13-10, 24-5, 24-6
GPAEN signal
control, 13-3, 13-6, 14-4
description, 2-8
usage, 13-10, 14-9, 14-17, 24-6
GPALE signal
control, 13-3, 13-6
description, 2-8
usage, 13-7, 24-6
GPALEOFF register, 13-6
GPALEW register, 13-6
GPBHE
signal
control, 13-3, 13-6
description, 2-8
usage, 13-19
GPCS7
–GPCS0 signals
configuration, 3-13, 4-5, 4-9, 4-15, 4-19
control, 3-10, 12-3, 13-3, 13-5, 13-6, 16-2, 17-1
description, 2-11
usage, 3-10, 12-3, 13-7, 24-4
GPCSDW register, 13-5
GPCSOFF register, 13-5
GPCSPW register, 13-5
GPCSQUAL register, 13-5
GPCSRT register, 13-5
GPCSx_SEL bit field, 12-3, 13-3, 16-1, 17-1
GPD15–GPD0 signals
description, 2-8
usage, 12-9, 13-10, 14-9, 24-6, 24-10
GPDACK3
–GPDACK0 signals
control, 13-3, 13-6, 14-4
description, 2-8
usage, 14-3
GPDBUFOE
signal
control, 13-3, 13-6
description, 2-8
usage, 13-4
GP-DMA Channel x Extended Page (GPDMAEXTPGx)
register
function, 14-4
usage, 14-11, 14-12
GP-DMA Channel x Extended Transfer Count
(GPDMAEXTTCx) register
function, 14-5
GP-DMA Channel x Next Address High
(GPDMANXTADDHx) register
function, 14-5, 14-6
usage, 14-15, 14-18
GP-DMA Channel x Next Address Low
(GPDMANXTADDLx) register
function, 14-5, 14-6
usage, 14-15, 14-18
GP-DMA Channel x Next Transfer Count High
(GPDMANXTTCHx) register
function, 14-6
usage, 14-15, 14-18
GP-DMA Channel x Next Transfer Count Low
(GPDMANXTTCLx) register
function, 14-6
usage, 14-15, 14-18
GP-DMA Control (GPDMACTL) register
function, 5-6, 14-4
usage, 5-8, 14-10, 14-18, 14-20
GP-DMA controller
addressing GP-DMA channels, 14-11
16-bit channel address generation (table), 14-12
8-bit channel address generation (table), 14-12
enhanced GP-DMA mode, 14-12
normal GP-DMA mode, 14-11
block diagram (figure), 14-2
bus cycles, 14-16
cycle types (table), 14-16
GP bus I/O to SDRAM, 14-16
read in demand transfer mode (figure), 14-16
read transfer (figure), 14-13
read transfer with cache hit (figure), 14-17
verify transfer (figure), 14-14
write transfer (figure), 14-14
channel mapping, 14-10
channel mapping (table), 14-10
clocking considerations, 14-18
example configurations, 14-19
16-bit channel in enhanced mode, 14-21
16-bit channel in normal mode, 14-20
8-bit channel in enhanced mode, 14-20
8-bit channel in normal mode, 14-19
fly-by transfers, 14-8
GP bus echo mode, 14-17
GP bus timing, 13-11
GP-DMA initiators, 14-9
external I/O devices, 14-9
external memory-mapped I/O devices, 14-10
internal UARTs, 14-9
GP-DMA transfer modes
automatic initialization control, 14-14
block transfer mode, 14-13
buffer chaining, 14-15
demand transfer mode, 14-12
priority, 14-15
single transfer mode, 14-12
transfer types, 14-13
GP-DMA transfers, 14-8
initialization, 14-19
initiator, 14-8
initiator/target combinations supported (table), 14-9
interrupts, 14-18
latency, 14-18
nonpreemptive latency, 14-18
preemptive latency, 14-19