Cypress EZ-USB FX3 - Page 302

EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 302
GPIF_CONFIG
0xE0014000
10.7.1 GPIF_CONFIG (continued)
13 DATA_COMP_TOGGLE 0 Comparator outputs true when bits match a target value.
1 Comparator outputs true when any of the unmasked bits change value.
12 CTRL_COMP_TOGGLE 0 Comparator outputs true when bits match a target value.
1 Comparator outputs true when any of the unmasked bits change value.
11 ADDR_COMP_TOGGLE 0 Comparator outputs true when bits match a target value.
1 Comparator outputs true when any of the unmasked bits change value.
10 ENDIAN Endianness of interface when PP_MODE==0
0 Little Endian
1 Big Endian
8 SYNC 0 Operate in asynchronous mode.
1 Operate in synchronous mode.
These mode have different clocking structures.
GPIF_CONFIG.SYNC should be set to indicate synchronous or Asynchronous MODE before pro-
gramming GPIF_BUS_CONFIG.DLE* and GPIF_BUS_CONFIG.ALE*
7 DOUT_POP_EN 0 rq_pop is a separate beta
1 Use update_dout (alpha) to also trigger rq_pop (which is normally beta)
6 DDR_MODE 0 Select 1X clock as the core clock
1 Select 2X clock as the core clock
5CLK_OUT Indicates whether to drive CLK pin with GPIF clock. No effect when CLK_SOURCE = 0 or PMMC
mode.
0 Do not output clock on CLK pin (typical of async mode)
1 Output clock on CLK pin (typical of sync master mode)
4 CLK_SOURCE Indicates whether clock is sourced from GCTL or pin. Has no effect in PMMC mode.
0 External clock input on CLK pin
1 Internal clock generated from GCTL
3 CLK_INVERT 0 Normal clock polarity (clock on positive edge)
1 Inverted clock polarity (clock on negative edge)
2 DATA_COMP_ENABLE 0 Disable the data comparator
1 Enable the data comparator
1 ADDR_COMP_ENABLE 0 Disable the address comparator
1 Enable the address comparator
0 CTRL_COMP_ENABLE 0 Disable the control comparator
1 Enable the control comparator