EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 304
GPIF_BUS_CONFIG
0xE0014004
10.7.2 GPIF_BUS_CONFIG (continued)
19:18 DRQ_MODE[1:0] 0 Assert DRQ on deassertion of DACK
1 Assert DRQ on assertion of DACK
2 Deassert DRQ on deassertion of DACK
3 Deassert DRQ on assertion of DACK
17 ALE_PRESENT CTRL[10] is ALE used to latch address from the DQ lines.
16 CNTR_PRESENT CTRL[9] is connected to the selected control counter bit instead of a control signal
15 FIO1_PRESENT CTRL[8] is to be treated as I/O that is driven out when the alpha specified in FIO1_CONF is asserted
(ignore CTRL_BUS_DIRECTION)
14 FIO0_PRESENT CTRL[7] is to be treated as I/O that is driven out when the alpha specified in FIO0_CONF is asserted
(ignore CTRL_BUS_DIRECTION)
13 DRQ_PRESENT CTRL[4] is directly influenced by CTRL[3]/DACK as defined by DRQ_MODE
This setting also overrides the CTRL_BUS_SELECT selection for this pin, in favor of betas 'assert
drq' and 'deassert_drq'
12 OE_PRESENT CTRL[2] is OE and should be used to tristate DQ lines.
If WE_PRESENT = 1 also, then OE will take precedence over WE. In other words, when WE is
asserted, then output drivers are off, regardless of value of OE input.
11 DLE_PRESENT CTRL[1] is DLE and should be used to latch data from DQ lines
Can be used together with WE_PRESENT
10 WE_PRESENT CTRL[1] is WE and should be used to disable DQ drivers
Can be used together with DLE_PRESENT
9 CE_PRESENT CTRL[0] is CE and should be used to disable DQ drivers
8:5 ADR_CTRL[3:0] Number of control lines overridden by address lines. Control signals CTRL[15] to CTRL[16-ADR_C-
TRL] are not connected to pins. Instead those pins are designated as address signals. Which
address signals depends on the other mode fields above. In other words: if ADR_CTRL = 0 all CTRL
lines are connected to pins, if ADR_CTRL = 1, CTRL[15] is not connected and so on.
4MUX_MODE 0 Address and data are separate lines.
1 Address is sampled from DQ, time multiplexed with data.
3:2 BUS_WIDTH[1:0] 0 DQ is 8b wide
1 DQ is 16b wide
2 DQ is 24b wide
3 DQ is 32b wide
1:0 PIN_COUNT[1:0] Number of pins allocated to GPIF interface. Needs to be consistent with GCTL_IOMATRIX:
0 47-pin interface
1 43-pin interface
2 35-pin interface
3 31-pin interface
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