Index
Index-4 Élan™SC520 Microcontroller User’s Manual
BR/TC signal
control, 25-4
description, 2-12
BSY bit field, 22-7
Buffer Chaining Control (GPDMABCCTL) register
function, 14-5
usage, 14-15
Buffer Chaining Interrupt Enable (GPDMABSINTENB)
register
function, 14-5
Buffer Chaining Status (GPDMABCSTA) register
function, 14-5
Buffer Chaining Valid (GPDMABCVAL) register
function, 14-5
usage, 14-15
bus arbitration.
See
system arbitration.
Bus Grant signals.
See
GNT4–GNT0 signals.
Bus Request signals.
See
REQ4–REQ0 signals.
BUS_MAS bit field, 9-11
BUS_NUM bit field, 9-10
BUS_PARK_SEL bit field, 8-10, 8-22
Bypass (BPR) register
function, 25-2
usage, 25-4
C
cache.
See
Am5
x
86® CPU.
CACHE_WR_MODE bit field, 7-4, 8-6
cacheability control, 3-12
CAS_LAT bit field, 10-20, 10-31
CBAR register, 4-2
CBE3
–CBE0 signals
description, 2-6
usage, 2-7
CF_DRAM
signal
control, 24-2
description, 2-12
usage, 10-19, 24-1, 24-3, 24-12
CF_ROM_GPCS
signal
control, 24-2
description, 2-12
usage, 10-19, 24-1, 24-4, 24-5, 24-6, 24-12
CFG2–CFG0 signals
description, 2-13
usage, 2-6, 6-4, 6-6, 11-3, 12-2, 12-7, 12-14, 24-1
CFG3 signal
description, 2-13
usage, 16-1
CH3_ALT_SIZE bit field, 14-21
Chip Select Pin Function Select (CSPFS) register
function, 12-5, 13-6, 16-2, 17-2, 23-4
usage, 12-3, 13-3, 13-22, 16-1, 17-1, 23-5
chip selects.
See
GPCS7–GPCS0 signals.
Class Code/Revision ID (PCICCREVID) register
function, 9-8
Clear To Send signals.
See
CTS2–CTS1 signals.
CLK_INV_ENB bit field, 22-5
CLK_PIN_DIR bit field, 5-3, 5-9, 16-1, 16-6, 16-7
CLK_PIN_ENB bit field, 5-9
CLK_SEL bit field, 5-8, 22-7
CLK_SRC bit field, 5-8, 21-10
CLK_TST_SEL bit field, 5-9
CLKMEMIN signal
description, 2-5
usage, 10-6, 10-7, 10-11
CLKMEMOUT signal
description, 2-5
usage, 10-6, 10-7, 10-11
CLKPCIIN signal
description, 2-6
usage, 9-5
CLKPCIOUT signal
description, 2-7
usage, 5-5, 9-2, 9-5, 9-6
CLKSEL register, 5-6, 23-4
CLKTEST signal
control, 5-3, 5-6, 16-1, 16-2
description, 2-10
usage, 5-9
CLKTIMER signal
control, 5-3, 5-6, 16-1, 16-2
description, 2-10
usage, 5-8, 5-9, 16-6, 16-7
clock generation and control
block diagram (figure), 5-2
CLKTEST clock routing (figure), 5-9
CLKTEST signal, 5-9
CLKTIMER signal, 5-9
clock distribution (figure), 5-3
clock sources (figure), 5-2
clock startup and lock times (table), 5-2
initialization, 5-9
internal clocks, 5-7
CPU, 5-7
general-purpose (GP) bus, 5-7
general-purpose (GP) timers, 5-8
GP-DMA controller, 5-8
PCI bus, 5-7
programmable interval timer (PIT), 5-8
real-time clock (RTC), 5-8
ROM/Flash interface, 5-7
SDRAM controller, 5-7
software timer, 5-8
synchronous serial interface (SSI), 5-8
UART serial ports, 5-8
watchdog timer, 5-8
operation, 5-7
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