Index
Élan™SC520 Microcontroller User’s Manual Index-5
PLL lock time (table), 5-2
PLLs, 5-7
registers, 5-6
signal descriptions, 2-10
system design, 5-3
bypassing 32.768-kHz oscillator (figure), 5-5
bypassing 33-MHz oscillator (figure), 5-6
bypassing internal oscillators, 2-10, 5-5
clock pin loading, 5-4
crystal selection, 5-4
shared signals (table), 5-3
timing error and clock accuracy (table), 5-5
Clock Select (CLKSEL) register
function, 5-6, 16-2, 21-3, 23-4
usage, 5-3, 5-9, 16-1, 16-6, 16-7
CMDACK signal
control, 25-4
description, 2-12
CNCR_MODE_ENB bit field, 8-3, 8-22, 24-10
code execution control, 3-12
Code Fetch ROM/GPCS signal.
See
CF_ROM_GPCS
signal.
Code Fetch SDRAM signal.
See
CF_DRAM signal.
Column Address Strobe signals.
See
SCASA–SCASB
signals.
Command Acknowledge signal.
See
CMDACK signal.
Command or Byte-Enable Bus signals.
See
CBE3–
CBE0
signals.
COMPTIM bit field, 14-9
configuration
signal descriptions, 2-13
Configuration Base Address (CBAR) register
function, 4-2
usage, 3-4, 4-9, 4-11, 4-17, 4-20
Configuration Input 3 signal.
See
CFG3 signal.
Configuration Input signals.
See
CFG2–CFG0 signals.
configuration RAM
function, 20-7
CONT_CMP bit field, 17-4
CPU.
See
Am5
x
86® CPU.
CPU bus arbitration.
See
system arbitration.
CPU_PRI bit field, 8-8
CPU_RST bit field, 6-4, 6-7
CPUCTL register, 7-1
CSPFS register, 23-4
CTR_MODE bit field, 16-4
CTS2
–CTS1 signals
control, 13-6, 21-2, 21-3, 21-4
description, 2-9, 21-6
usage, 21-2, 21-9
customer service, iii
D
data buses
boot device configuration, 12-7, 12-14
CFG2 pinstrap, 2-13
general-purpose (GP) bus data bus, 2-8
loading, 10-9, 12-3, 13-4
PCI data bus, 2-6
ROM/Flash controller data bus, 2-6
ROM/Flash controller data bus connection options
(table), 12-1
SDQMx signal behavior, 10-6
SDRAM controller data bus, 2-5
shared buses, 13-10
voltage isolation, 12-3
Data Carrier Detect signals.
See
DCD2–DCD1 signals.
Data Input/Output Mask signals.
See
SDQM3–SDQM0
signals.
Data Set Ready signals.
See
DSR2–DSR1 signals.
data sheet, xxiv
Data Strobe signal.
See
DATASTRB signal.
Data Terminal Ready signals.
See
DTR2–DTR1
signals.
DATASTRB signal
control, 24-2
description, 2-12
usage, 10-19, 24-1, 24-3, 24-4, 24-12
DBCTL register, 11-4
DCD2
–DCD1 signals
control, 13-6, 21-2, 21-3, 21-4
description, 2-9, 21-6
usage, 21-2, 21-9
DCTS bit field, 21-6
DDCD bit field, 21-6
DDSR bit field, 21-6
DEBUG_ENTER signal
description, 2-13
usage, 26-2
debugging.
See
chip test and debugging.
See also
system test and debugging.
See also
AMDebug™ technology.
Device Identification (DID) register
format, 25-14
function, 25-2
usage, 25-4, 25-13
Device Select signal.
See
DEVSEL signal.
Device/Vendor ID (PCIDEVID) register
function, 9-8
DEVICE_NUM bit field, 9-10
DEVSEL
signal
control, 9-8
description, 2-7
timing, 9-19
usage, 9-3, 9-19
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