EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F 8
Contents
7.8 Initialization and Configuration of GPIF II Block ...................................................................151
7.8.1 GPIF II State Machine Control ..................................................................................151
7.9 Performing Read and Write Operations Using GPIF II .........................................................151
7.10 DMA Channel Creation in FX3 Firmware to Perform GPIF II to USB Data Transfers ..........153
7.11 GPIF II State Machine to Read Data into a Socket ..............................................................153
7.12 DMA Channel Creation in FX3 Firmware to Perform USB to GPIF II Data Transfers ..........154
7.13 GPIF II State Machine to Drive Data from Socket as Data Source ......................................155
7.13.1 Alpha Values .............................................................................................................156
7.14 GPIF II Read and Write over Registers ................................................................................156
7.15 Implementing Synchronous Slave FIFO Interface ................................................................158
7.16 Synchronous Slave FIFO Access Sequence and Interface Timing ......................................161
7.16.1 Synchronous Slave FIFO Read Sequence Description ............................................162
7.16.2 Synchronous Slave FIFO Write Sequence Description ............................................164
7.16.3 Slave FIFO Interface Logical Diagram ......................................................................165
7.16.4 GPIF II State Machine of Slave FIFO Interface.........................................................165
8. Low Performance Peripherals (LPP) 167
8.1 I2C Interface .........................................................................................................................168
8.1.1 I2C Block Features....................................................................................................168
8.1.2 I2C Interface Overview..............................................................................................169
8.2 FX3 I2C Operations Overview ..............................................................................................170
8.2.1 Reset and Initialization ..............................................................................................170
8.2.2 Preamble...................................................................................................................170
8.2.3 Data Transfer ............................................................................................................170
8.2.3.1 Programming Model ..................................................................................170
8.2.3.2 Register-Based I2C Transfers ...................................................................171
8.2.3.3 DMA-Based I2C Transfers ........................................................................171
8.2.3.4 Starting a Transaction ...............................................................................171
8.2.3.5 Terminating Transactions: Software and Hardware Aborts.......................172
8.2.3.6 Multimaster Arbitration...............................................................................172
8.2.3.7 Error Conditions.........................................................................................172
8.2.4 Examples ..................................................................................................................172
8.2.4.1 Initialize I2C Block .....................................................................................172
8.2.4.2 Configure I2C Block...................................................................................173
8.2.4.3 Reads and Writes Using Register Transfers .............................................173
8.2.4.4 Reads and Writes Using DMA Transfers...................................................174
8.3 Serial Peripheral Interface ....................................................................................................175
8.3.1 SPI Block Features ...................................................................................................175
8.3.2 SPI Interface Overview .............................................................................................176
8.3.3 FX3 SPI Operations Overview ..................................................................................177
8.3.3.1 Reset and Initialization ..............................................................................177
8.3.3.2 Modes Governing Transfers ......................................................................177
8.3.4 SSN Control Configurations ......................................................................................177
8.3.5 Data Transfers...........................................................................................................178
8.4 Programming Model .............................................................................................................178
8.4.1 Register-Based Transfers .........................................................................................178
8.4.2 DMA-Based Transfers...............................................................................................178
8.5 Examples ..............................................................................................................................179
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