4535 611 98931 iE33 Service Manual Page 100
CSIP Level 1 Theory of Operation: Bus Functions
Inter-Card Cage
Buses
Acquisition Control Bus
The Acquisition Control Bus provides a high-bandwidth interface between the Acquisition Card
Cage and the Platform Card Cage. It provides two unidirectional, five-channel LVDS data and
clock paths, reset and hold lines from the Platform Card Cage to the Acquisition Card Cage, and
link clock signal lines. The physical connections are between the FEC and the AVIO. The bus also
provides a low-noise bus structure to minimize EMI/RFI. It moves all control and ancillary data
movement (non-beamformed RF data).
RF Bus A/B
The RF Bus comprises two identical 28-bit bus structures (only 24 bits are used). RF data is
moved from the FEC to the DSC via this bus. There is no handshake provided for data transfers.
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