Philips iE33 - Front-End Buses

4535 611 98931 iE33 Service Manual Page 101
CSIP Level 1 Theory of Operation: Bus Functions
Front-End Buses FEP Bus
The FEP Bus is a static address, data, and control structure that provides access to various
resources on the NAIM, Channel Boards, and S/HSEL modules. This is a 16-bit extension of the
FEC local processor bus operating at 40 MHz.
FEC Bus
The FEC Bus provides real-time access to the Nile ASICs on the Channel Boards and the NAIM
for control and timing purposes. The bus architecture is a static address and data with additional
control signals for SDRAM access and control. The clock rate is 40 MHz.
SUM Bus Structure
The SUM Bus structure is composed of two identical bus paths of four segments, daisy-chained
between the Channel Boards. Each Channel Board sums its channels. It then sums its result with
the sum of the previous Channel Board and passes the result to the next Channel Board. Data
ends at the FEC. It can transport RF data at single or double rates. CW RF Doppler data may be
driven onto this bus by the NAIM. Clock rate is 32 or 64 MHz.
TIM Bus
Provides all PRI-PRI real-time control signals as required by the Nile ASIC and the NAIM CW
processing module. The control signals include transmit and receive coarse-delay control,
high-voltage rail selection, PRI reset, and skin-line identification. The clock rate is 32 MHz.