4535 611 98931 iE33 Service Manual Page 88
CSIP Level 1 Theory of Operation: Physical Structure
Front End Controller (FEC)
• Uses 40-MHz/32-MHz differential clocks and 8-MHz sync clock (all derived from NAIM)
• Contains an integrated Omni Motor Controller to control the S7-2omni transducer
• Contains a slot for the Galil Motor Controller PCB for 3D acquisition (not currently imple-
mented)
• Programs the Motor Controller with a motion profile for speed and position control
• AP&I power monitor control through FEP bus and utilized by FEC processor
• Monitors system temperature from sensors located on several modules in the card cage
• Physio functions
- Contains jacks for internal ECG input, external or high-level ECG input, Pulse/Aux1
input, Phono/Aux2 input, and ECG analog out or ECG trigger out
- Processes respiratory, pulse, phono, and auxiliary (from third-party equipment)
- Simultaneous acquisition and processing of four channels of physio data
- Data managed by FEC CPU
- Data sent to AVIO for storage in the Host CPU memory
• FEC processor is Motorolla 603a CPU processor
• Responsible for event timing signal set to control the beamformer signal path for each PRI
• Sends control data from FEC to the Channel Board, NAIM, and S/HSEL
• Sends TGC data from FEC to the TGC ASIC on the NAIM
• Accepts real-time RF data from Channel Boards on SUM bus A and SUM bus B
• FEC is I
2
C bus master for entire Acquisition Subsystem
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