4535 611 98931 iE33 Service Manual Page 89
CSIP Level 1 Theory of Operation: Physical Structure
• RF pre-processing: RF headers, low-pass filter, and line composition buffer to reorder output
lines to the DSC
• Contains serial LVDS host interface to the AVIO
• Configures the NAIM FPGA using the FEP bus (FPGA is a Field Programmable Gate Array: a
general purpose chip which can be programmed to carry out a specific hardware function.)
• Foot switch interface
• Sequencing in Krusty ASIC and controls beamformer operation
• RF sequencer responsible for controlling RF processor (Tigris FPGA)
• Drives the RF header bus and control signals to Tigris FPGA
• Signal path mode switching
Acquisition Frontplane (AqF)
• Provides connections and signal paths for the NAIM, FEC, and the Channel Boards
• Distributes power supply buses and clock signals to the NAIM, FEC, and Channel Boards
• Provides data bus, address bus, and clock termination networks
• Contains de-bounce circuit for foot switch to prevent accidental double depression
• Contains the Acquisition Control Bus, which is the interface to the Platform Card Cage
Channel Boards (CB)
• Four Channel Boards (A0 through A3), four Nile ASICs per board with 16 DAC transmit
each. Only eight DAC are used for each board.
• Channel Board transmit functions are not used for Matrix transducers
• Nile ASICs contain a transmit burst controller, waveform generator, waveform weighting, and
waveform pre-distortion.
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