B: Status model 2470 High Voltage SourceMeter Instrument
B-10 2470-901-01 Rev. A / May 2019
The instrument is operating at normal temperature levels and fully functional.
2777
The instrument temperature has reached a level in which source output and other
functionality will not be available.
2778
The instrument temperature has fallen to a level in which source output and other
functionality is now available.
The specified reading buffer is cleared (empty).
The specified reading buffer is full.
The source output has gone over the source limit level and is being limited.
5081
The source output has returned below the source limit level and is no longer being
limited.
Status Byte Register
The Status Byte Register monitors the registers and queues in the status model and generates
service requests (SRQs).
When bits are set in the status model registers and queues, they generate summary messages that
set or clear bits of the Status Byte Register. You can enable these bits to generate an SRQ.
Service requests (SRQs) instruct the controller that the instrument needs attention or that some event
has occurred. When the controller receives an SRQ, the controller can interrupt existing tasks to
perform tasks that address the request for service.
For example, you might program your instrument to send an SRQ when a specific instrument error
event occurs. To do this, you set the Status Request Enable bit 2 (EAV). In this example, the
following actions occur:
• The error event occurs.
• The error event is logged in the Error Queue.
• The Error Queue sets the EAV bit of the Status Byte Register.
• The EAV bits are summed.
• The RQS bit of the Status Byte Register is set.
• On a GPIB system, the SRQ line is asserted. On a VXI-11 or USB system, an SRQ event is
generated.
For an example of this, see the example code provided in SRQ on error (on page B-22
).
The summary messages from the status registers and queues set or clear the appropriate bits (B0,
B2, B3, B4, B5, and B7) of the Status Byte Register. These summary bits do not latch, and their
states (0 or 1) are solely dependent on the summary messages (0 or 1). For example, if the Standard
Event Register is read, its register will clear. As a result, its summary message resets to 0, which in
turn resets the ESB bit in the Status Byte Register.
The Status Byte Register also receives summary bits from itself, which sets the Master Summary
Status (MSS) bit.
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