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Avaya Definity SI - Page 2297

Avaya Definity SI
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SHDW-LNK (Memory Shadowing Link)
Issue 4 May 2002
10-1511555-233-123
2050 FAIL The Standby SPE Maintenance/Tape Processor released the
Standby SPE Processor with a request to perform the RAM
Checksum Test on Standby SPE Memory. The RAM checksum
was correct and the two special Standby SPE Memory locations
contain the same time stamp value as the one shadowed over
from the Active SPE; however, that time stamp value is
significantly different from the value of the Standby SPEs
Time-of-Day clock. This indicates that either the Active SPE
Time-of-Day clock has never been set (for example, at system
installation time) or that the Active SPE Time-of-Day clock was
set (with a significant change) while shadowing to the Standby
SPE was disabled.
1. Issue the refresh spe-standby command to put the Standby
SPE in Standby Mode. This command may have to be issued
multiple times. If the refresh spe-standby command
successfully completes 5 times without the Standby SPE
becoming labeled standby on the status system form, wait
20 minutes. This does not include cases where the command
completes with the terminal message line errors Refresh not
successful; use display errors to check for STBY-SPE
errors or Cannot interrupt Standby SPE while entering
maintenance mode; please try later. Issue the refresh
spe-standby command once more.
2. Issue the set time command and set the Time-of-Day clock.
3. Repeat the test.
PASS When the Shadow Link Test passes, the integrity of the Memory
Shadowing Link has been verified and as long as memory
shadowing is enabled, Standby SPE Memory is an up-to-date
reflection of Active SPE Memory. This test also provides a
positive indication of the functionality of Active SPE Memory, both
sets of Common Shadow Circuit, and Standby SPE Memory.
Table 10-572. TEST #318 Shadow Link Test Continued
Error
Code
Tes t
Result Description/Recommendation
Continued on next page

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