Avaya Definity SI - Page 2281

SHDW-LNK (Memory Shadowing Link)
Issue 4 May 2002
10-1495555-233-123
Please refer to the DUPINT, SHDW-CIR, MEM-BD, PROCR, PR-MAINT, and
STBY-SPE Maintenance documentation for more detailed descriptions of these
components.
Figure 10-88. SHDW-LNK Interactions (High or Critical Reliability)
Figure Notes:
1. Fiber optic connection (front of TN792)
2. Processor Interface circuit pack
ICC-A
ICC-B
ICC-C
(SCC only)
MBUS
MBUS
Packet
Bus
Packet
Bus
TDM Bus A
TDM Bus A
Pkt ctrl
Pkt ctrl
B
c
arrier
A
c
arrier
DUP-A
to
MTP-B
DUP-A
to
MTP-B
SPE select lead
SPE select lead
Tone-Clock select lead
Tone-Clock select lead
1
2
2
T
O
N
E
C
L
O
C
K
TDM Bus B
TDM Bus B
P
R
O
C
E
S
S
O
R
M
E
M
O
R
Y
Shadow
Shadow
Serial
Serial
Control
Control
D
U
P
I
N
T
DUP-
DUP
DUP-
DUP
N
E
T
P
K
T
P
I
1
P
I
1
D
U
P
I
N
T
P
R
O
C
E
S
S
O
R
M
E
M
O
R
Y
N
E
T
P
K
T
DUP-A to
MTP-A
SAT
cydfdicp LJK 042699
T
O
N
E
C
L
O
C
K