Home
ST
Microcontrollers
STM32F40 Series
ST STM32F40 Series User Manual
4
of 1
of 1 rating
1422 pages
Give review
Manual
Specs
To Next Page
To Next Page
To Previous Page
To Previous Page
RM0090
USB on-the-go high-speed (OTG_HS)
Doc ID 018909 Rev 4
1276/1422
Figure 392.
Normal interrupt OUT/IN transactions - Sla
ve mode
●
Interrupt ser
vice routine for interrupt OUT/IN transactions
a) Interrupt
OUT
Unmask (NAK/TXERR/STALL/XFRC/FRMOR)
if (
XFRC
)
{
Reset Error Count
Mask
ACK
De-allocate Channel
}
else
if (
STALL
or
FRMOR
)
{
1275
1277
Table of Contents
Table 1. Applicable Products
1
Table of Contents
2
Documentation Conventions
47
List of Abbreviations for Registers
47
Glossary
48
Peripheral Availability
48
Memory and Bus Architecture
49
System Architecture
49
Figure 1. System Architecture for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx Devices
50
Figure 2. System Architecture for Stm32F42Xxx and Stm32F43Xxx Devices
50
S0: I-Bus
51
S1: D-Bus
51
S2: S-Bus
51
S3, S4: DMA Memory Bus
51
S5: DMA Peripheral Bus
51
S6: Ethernet DMA Bus
51
S7: USB OTG HS DMA Bus
51
Busmatrix
51
AHB/APB Bridges (APB)
52
Memory Organization
52
Memory Map
52
Table 2. Stm32F4Xx Register Boundary Addresses
52
Embedded SRAM
55
Flash Memory Overview
55
Bit Banding
55
Boot Configuration
56
Table 3. Boot Modes
56
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap
57
Embedded Flash Memory Interface
59
Introduction
59
Main Features
59
Figure 3. Flash Memory Interface Connection Inside System Architecture
59
Embedded Flash Memory
60
Table 5. Flash Module Organization (Stm32F40X and Stm32F41X)
60
Read Interface
61
Relation between CPU Clock Frequency and Flash Memory Read Time
61
Table 6. Flash Memory Organization (Stm32F42X and Stm32F43X)
61
Number of Wait States According to CPU Clock (HCLK) Frequency
62
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
63
Figure 4. Sequential 32-Bit Instruction Execution
64
Erase and Program Operations
65
Unlocking the Flash Control Register
65
Program/Erase Parallelism
66
Erase
66
Table 8. Program/Erase Parallelism
66
Programming
67
Interrupts
68
Option Bytes
68
Description of User Option Bytes
68
Table 9. Flash Interrupt Request
68
Table 10. Option Byte Organization
68
Table 11. Description of the Option Bytes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
69
Table 12. Description of the Option Bytes (Stm32F42Xxx and Stm32F43Xxx)
70
Programming User Option Bytes
71
Read Protection (RDP)
72
Write Protections
73
Table 13. Access Versus Read Protection Level
73
Figure 5. RDP Levels
73
One-Time Programmable Bytes
74
Table 14. OTP Area Organization
74
Flash Interface Registers
75
Flash Access Control Register (FLASH_ACR)
75
Flash Key Register (FLASH_KEYR)
77
Flash Option Key Register (FLASH_OPTKEYR)
77
Flash Status Register (FLASH_SR)
78
Flash Control Register (FLASH_CR) for
79
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
79
Stm32F42Xxx and Stm32F43Xxx
80
Flash Option Control Register (FLASH_OPTCR)
82
Flash Option Control Register (FLASH_OPTCR1)
83
For Stm32F42Xxx and Stm32F43Xxx
83
Flash Interface Register Map
84
Table 15. Flash Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
84
Table 16. Flash Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
84
CRC Calculation Unit
86
CRC Introduction
86
CRC Main Features
86
CRC Functional Description
86
Figure 6. CRC Calculation Unit Block Diagram
86
CRC Registers
87
Data Register (CRC_DR)
87
Independent Data Register (CRC_IDR)
87
Control Register (CRC_CR)
88
CRC Register Map
88
Table 17. CRC Calculation Unit Register Map and Reset Values
88
Power Controller (PWR)
89
Power Supplies
89
Figure 7. Power Supply Overview
89
Independent A/D Converter Supply and Reference Voltage
90
Battery Backup Domain
90
Voltage Regulator
92
Figure 8. Backup Domain
92
Power Supply Supervisor
94
Power-On Reset (Por)/Power-Down Reset (PDR)
94
Brownout Reset (BOR)
94
Figure 9. Power-On Reset/Power-Down Reset Waveform
94
Programmable Voltage Detector (PVD)
95
Figure 10. BOR Thresholds
95
Low-Power Modes
96
Figure 11. PVD Thresholds
96
Slowing down System Clocks
97
Peripheral Clock Gating
97
Table 18. Low-Power Mode Summary
97
Sleep Mode
98
Table 19. Sleep-Now Entry and Exit
98
Stop Mode
99
Table 20. Sleep-On-Exit Entry and Exit
99
Table 21. Stop Operating Modes
100
Table 22. Stop Mode Entry and Exit
100
Standby Mode
101
Table 23. Standby Mode Entry and Exit
101
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
102
Power Control Registers
105
PWR Power Control Register (PWR_CR)
105
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
105
PWR Power Control Register (PWR_CR)
106
For Stm32F42Xxx and Stm32F43Xxx
106
PWR Power Control/Status Register (PWR_CSR)
108
PWR Register Map
109
Table 24. PWR - Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
109
Table 25. PWR - Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
110
Reset and Clock Control for (RCC)
111
Reset
111
System Reset
111
Power Reset
112
Figure 12. Simplified Diagram of the Reset Circuit
112
Backup Domain Reset
113
Clocks
113
Figure 13. Clock Tree
114
HSE Clock
116
Figure 14. HSE/ LSE Clock Sources
116
HSI Clock
117
PLL Configuration
117
LSE Clock
118
LSI Clock
118
System Clock (SYSCLK) Selection
118
Clock Security System (CSS)
118
RTC/AWU Clock
119
Watchdog Clock
120
Clock-Out Capability
120
Internal/External Clock Measurement Using TIM5/TIM11
120
Figure 15. Frequency Measurement with TIM5 in Input Capture Mode
121
Figure 16. Frequency Measurement with TIM11 in Input Capture Mode
122
RCC Registers
123
RCC Clock Control Register (RCC_CR)
123
RCC PLL Configuration Register (RCC_PLLCFGR)
125
RCC Clock Configuration Register (RCC_CFGR)
127
RCC Clock Interrupt Register (RCC_CIR)
129
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
132
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
134
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
135
RCC APB1 Peripheral Reset Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB1RSTR)
135
RCC APB1 Peripheral Reset Register for
138
Stm32F42Xxx and Stm32F43Xxx (RCC_APB1RSTR)
138
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
141
RCC APB2 Peripheral Reset Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB2RSTR)
143
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
145
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
147
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
148
RCC APB1 Peripheral Clock Enable Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB1ENR)
148
RCC APB1 Peripheral Clock Enable Register for Stm32F42Xxx and Stm32F43Xxx(RCC_APB1ENR)
151
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
154
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
154
RCC APB2 Peripheral Clock Enable Register for Stm32F42Xxx and Stm32F43Xxx(RCC_APB2ENR)
156
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx (RCC_AHB1LPENR)
158
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_AHB1LPENR)
161
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
163
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
164
RCC APB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx (RCC_APB1LPENR)
165
RCC APB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB1LPENR)
168
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB2LPENR)
171
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB2LPENR)
173
RCC Backup Domain Control Register (RCC_BDCR)
175
RCC Clock Control & Status Register (RCC_CSR)
176
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
178
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
179
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
180
RCC Register Map
181
Table 26. RCC Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
181
Table 27. RCC Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
183
General-Purpose I/Os (GPIO)
185
GPIO Introduction
185
GPIO Main Features
185
GPIO Functional Description
185
Figure 17. Basic Structure of a Five-Volt Tolerant I/O Port Bit
186
General-Purpose I/O (GPIO)
187
Table 28. Port Bit Configuration Table
187
I/O Pin Multiplexer and Mapping
188
Table 29. Flexible SWJ-DP Pin Assignment
189
Figure 18. Selecting an Alternate Function on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
190
I/O Port Control Registers
191
Figure 19. Selecting an Alternate Function on Stm32F42Xxx and Stm32F43Xxx
191
I/O Port Data Registers
192
I/O Data Bitwise Handling
192
GPIO Locking Mechanism
192
I/O Alternate Function Input/Output
193
External Interrupt/Wakeup Lines
193
Input Configuration
193
Output Configuration
194
Figure 20. Input Floating/Pull Up/Pull down Configurations
194
Alternate Function Configuration
195
Figure 21. Output Configuration
195
Figure 22. Alternate Function Configuration
195
Analog Configuration
196
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
196
Port Pins
196
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
196
Figure 23. High Impedance-Analog Configuration
196
Selection of RTC_AF1 and RTC_AF2 Alternate Functions
197
Table 30. RTC_AF1 Pin
197
GPIO Registers
198
GPIO Port Mode Register (Gpiox_Moder) (X = A..I
198
Table 31. RTC_AF2 Pin
198
GPIO Port Output Type Register (Gpiox_Otyper)
199
(X = a
199
GPIO Port Output Speed Register (Gpiox_Ospeedr)
199
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
199
GPIO Port Input Data Register (Gpiox_Idr) (X = A..I
200
GPIO Port Output Data Register (Gpiox_Odr) (X = A..I
200
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A..I
201
GPIO Port Configuration Lock Register (Gpiox_Lckr)
201
(X = a
201
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = A..I
202
(X = a
203
GPIO Register Map
203
Table 32. GPIO Register Map and Reset Values
203
System Configuration Controller (SYSCFG)
206
I/O Compensation Cell
206
SYSCFG Registers
206
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
206
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
207
For Stm32F42Xxx and Stm32F43Xxx
207
SYSCFG External Interrupt Configuration Register 1
208
(Syscfg_Exticr1)
208
SYSCFG External Interrupt Configuration Register 2
209
(Syscfg_Exticr2)
209
(Syscfg_Exticr3)
209
SYSCFG External Interrupt Configuration Register 4
210
(Syscfg_Exticr4)
210
Compensation Cell Control Register (SYSCFG_CMPCR)
210
SYSCFG Register Maps
211
Table 33. SYSCFG Register Map and Reset Values Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
211
Table 34. SYSCFG Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
212
DMA Controller (DMA)
213
DMA Introduction
213
DMA Main Features
213
DMA Functional Description
215
General Description
215
Figure 24. DMA Block Diagram
215
Figure 25. System Implementation of the Two DMA Controllers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
216
DMA Transactions
217
Figure 26. System Implementation of the Two DMA Controllers (Stm32F42Xxx and Stm32F43Xxx)
217
Channel Selection
218
Table 35. DMA1 Request Mapping
218
Figure 27. Channel Selection
218
Arbiter
219
Table 36. DMA2 Request Mapping
219
DMA Streams
220
Source, Destination and Transfer Modes
220
Table 37. Source and Destination Address
220
Figure 28. Peripheral-To-Memory Mode
221
Figure 29. Memory-To-Peripheral Mode
222
Pointer Incrementation
223
Figure 30. Memory-To-Memory Mode
223
Circular Mode
224
Double Buffer Mode
224
Programmable Data Width, Packing/Unpacking, Endianess
225
Table 38. Source and Destination Address Registers in Double Buffer Mode (DBM=1)
225
Table 39. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
226
Table 40. Restriction on NDT Versus PSIZE and MSIZE
226
Single and Burst Transfers
227
Fifo
227
Figure 31. FIFO Structure
228
Table 41. FIFO Threshold Configurations
229
DMA Transfer Completion
230
DMA Transfer Suspension
231
Flow Controller
231
Summary of the Possible DMA Configurations
232
Table 42. Possible DMA Configurations
232
Stream Configuration Procedure
233
Error Management
234
DMA Interrupts
235
DMA Registers
235
DMA Low Interrupt Status Register (DMA_LISR)
235
Table 43. DMA Interrupt Requests
235
DMA High Interrupt Status Register (DMA_HISR)
236
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
237
DMA High Interrupt Flag Clear Register (DMA_HIFCR)
237
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0
239
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0
242
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0
242
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar) (X = 0
243
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar) (X = 0
243
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0
244
DMA Register Map
245
Table 44. DMA Register Map and Reset Values
245
Interrupts and Events
249
Nested Vectored Interrupt Controller (NVIC)
249
NVIC Features
249
Systick Calibration Value Register
249
Interrupt and Exception Vectors
249
External Interrupt/Event Controller (EXTI)
249
Table 45. Vector Table for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
250
Table 46. Vector Table for Stm32F42Xxx and Stm32F43Xxx
253
EXTI Main Features
257
EXTI Block Diagram
257
Wakeup Event Management
257
Figure 32. External Interrupt/Event Controller Block Diagram
257
Functional Description
258
External Interrupt/Event Line Mapping
259
Figure 33. External Interrupt/Event GPIO Mapping
259
EXTI Registers
260
Interrupt Mask Register (EXTI_IMR)
260
Event Mask Register (EXTI_EMR)
260
Rising Trigger Selection Register (EXTI_RTSR)
260
Falling Trigger Selection Register (EXTI_FTSR)
261
Software Interrupt Event Register (EXTI_SWIER)
261
Pending Register (EXTI_PR)
262
EXTI Register Map
262
Table 47. External Interrupt/Event Controller Register Map and Reset Values
262
Analog-To-Digital Converter (ADC)
264
ADC Introduction
264
ADC Main Features
264
ADC Functional Description
264
Figure 34. Single ADC Block Diagram
265
ADC On-Off Control
266
ADC Clock
266
Channel Selection
266
Table 48. ADC Pins
266
Single Conversion Mode
267
Continuous Conversion Mode
267
Timing Diagram
268
Analog Watchdog
268
Figure 35. Timing Diagram
268
Scan Mode
269
Table 49. Analog Watchdog Channel Selection
269
Figure 36. Analog Watchdog's Guarded Area
269
Injected Channel Management
270
Figure 37. Injected Conversion Latency
270
Discontinuous Mode
271
Data Alignment
272
Channel-Wise Programmable Sampling Time
272
Figure 38. Right Alignment of 12-Bit Data
272
Figure 39. Left Alignment of 12-Bit Data
272
Figure 40. Left Alignment of 6-Bit Data
272
Conversion on External Trigger and Trigger Polarity
273
Table 50. Configuring the Trigger Polarity
273
Table 51. External Trigger for Regular Channels
274
Fast Conversion Mode
275
Table 52. External Trigger for Injected Channels
275
Data Management
276
Using the DMA
276
Managing a Sequence of Conversions Without Using the DMA
276
Conversions Without DMA and Without Overrun Detection
277
Multi ADC Mode
277
Figure 41. Multi ADC Block Diagram
278
Injected Simultaneous Mode
280
Regular Simultaneous Mode
281
Figure 42. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
281
Figure 43. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
281
Figure 44. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
282
Figure 45. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
282
Interleaved Mode
283
Figure 46. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
283
Alternate Trigger Mode
284
Figure 47. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
284
Figure 48. Alternate Trigger: Injected Group of each ADC
285
Combined Regular/Injected Simultaneous Mode
286
Figure 49. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
286
Figure 50. Alternate Trigger: Injected Group of each ADC
286
Combined Regular Simultaneous + Alternate Trigger Mode
287
Figure 51. Alternate + Regular Simultaneous
287
Temperature Sensor
288
Figure 52. Case of Trigger Occurring During Injected Conversion
288
Figure 53. Temperature Sensor and VREFINT Channel Block Diagram
289
Battery Charge Monitoring
290
ADC Interrupts
290
Table 53. ADC Interrupts
290
ADC Registers
291
ADC Status Register (ADC_SR)
291
ADC Control Register 1 (ADC_CR1)
292
ADC Control Register 2 (ADC_CR2)
294
ADC Sample Time Register 1 (ADC_SMPR1)
297
ADC Sample Time Register 2 (ADC_SMPR2)
297
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
298
ADC Watchdog Higher Threshold Register (ADC_HTR)
298
ADC Watchdog Lower Threshold Register (ADC_LTR)
298
ADC Regular Sequence Register 1 (ADC_SQR1)
299
ADC Regular Sequence Register 2 (ADC_SQR2)
299
ADC Regular Sequence Register 3 (ADC_SQR3)
300
ADC Injected Sequence Register (ADC_JSQR)
300
ADC Injected Data Register X (Adc_Jdrx) (X= 1
301
ADC Regular Data Register (ADC_DR)
301
ADC Common Status Register (ADC_CSR)
303
ADC Common Control Register (ADC_CCR)
304
11.13.17 ADC Common Regular Data Register for Dual and Triple Modes
307
(Adc_Cdr)
307
11.13.18 ADC Register Map
307
Table 54. ADC Global Register Map
307
Table 55. ADC Register Map and Reset Values for each ADC
308
Table 56. ADC Register Map and Reset Values (Common ADC Registers)
309
Digital-To-Analog Converter (DAC)
310
DAC Introduction
310
DAC Main Features
310
Table 57. DAC Pins
311
Figure 54. DAC Channel Block Diagram
311
DAC Functional Description
312
DAC Channel Enable
312
DAC Output Buffer Enable
312
DAC Data Format
312
Figure 55. Data Registers in Single DAC Channel Mode
312
DAC Conversion
313
Figure 56. Data Registers in Dual DAC Channel Mode
313
Figure 57. Timing Diagram for Conversion with Trigger Disabled TEN = 0
313
DAC Output Voltage
314
DAC Trigger Selection
314
DMA Request
314
Table 58. External Triggers
314
Noise Generation
315
Figure 58. DAC LFSR Register Calculation Algorithm
315
Triangle-Wave Generation
316
Figure 59. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
316
Figure 60. DAC Triangle Wave Generation
316
Dual DAC Channel Conversion
317
Independent Trigger Without Wave Generation
317
Figure 61. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
317
Independent Trigger with Single LFSR Generation
318
Independent Trigger with Different LFSR Generation
318
Independent Trigger with Single Triangle Generation
318
Independent Trigger with Different Triangle Generation
319
Simultaneous Software Start
319
Simultaneous Trigger Without Wave Generation
319
Simultaneous Trigger with Single LFSR Generation
320
Simultaneous Trigger with Different LFSR Generation
320
Simultaneous Trigger with Single Triangle Generation
320
Simultaneous Trigger with Different Triangle Generation
321
DAC Registers
321
DAC Control Register (DAC_CR)
321
DAC Software Trigger Register (DAC_SWTRIGR)
324
DAC Channel1 12-Bit Right-Aligned Data Holding Register
324
(Dac_Dhr12R1)
324
DAC Channel1 12-Bit Left Aligned Data Holding Register
325
(Dac_Dhr12L1)
325
DAC Channel1 8-Bit Right Aligned Data Holding Register
325
(Dac_Dhr8R1)
325
DAC Channel2 12-Bit Right Aligned Data Holding Register
325
(Dac_Dhr12R2)
325
DAC Channel2 12-Bit Left Aligned Data Holding Register
326
(Dac_Dhr12L2)
326
DAC Channel2 8-Bit Right-Aligned Data Holding Register
326
(Dac_Dhr8R2)
326
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
326
DUAL DAC 12-Bit Left Aligned Data Holding Register
327
(Dac_Dhr12Ld)
327
DUAL DAC 8-Bit Right Aligned Data Holding Register
327
(Dac_Dhr8Rd)
327
DAC Channel1 Data Output Register (DAC_DOR1)
328
DAC Channel2 Data Output Register (DAC_DOR2)
328
DAC Status Register (DAC_SR)
328
DAC Register Map
329
Table 59. DAC Register Map
329
Digital Camera Interface (DCMI)
330
DCMI Introduction
330
DCMI Main Features
330
DCMI Pins
330
DCMI Clocks
330
Table 60. DCMI Pins
330
DCMI Functional Overview
331
Figure 62. DCMI Block Diagram
331
Figure 63. Top-Level Block Diagram
331
DMA Interface
332
DCMI Physical Interface
332
Table 61. DCMI Signals
332
Figure 64. DCMI Signal Waveforms
332
Table 62. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
333
Table 63. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
333
Table 64. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
333
Synchronization
334
Table 65. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
334
Figure 65. Timing Diagram
334
Capture Modes
336
Figure 66. Frame Capture Waveforms in Snapshot Mode
336
Crop Feature
337
Figure 67. Frame Capture Waveforms in Continuous Grab Mode
337
Figure 68. Coordinates and Size of the Window after Cropping
337
JPEG Format
338
Fifo
338
Figure 69. Data Capture Waveforms
338
Data Format Description
339
Data Formats
339
Monochrome Format
339
RGB Format
339
Table 66. Data Storage in Monochrome Progressive Video Format
339
Figure 70. Pixel Raster Scan Order
339
Ycbcr Format
340
DCMI Interrupts
340
Table 67. Data Storage in RGB Progressive Video Format
340
Table 68. Data Storage in Ycbcr Progressive Video Format
340
Table 69. DCMI Interrupts
340
DCMI Register Description
341
DCMI Control Register 1 (DCMI_CR)
341
DCMI Status Register (DCMI_SR)
343
DCMI Raw Interrupt Status Register (DCMI_RIS)
344
DCMI Interrupt Enable Register (DCMI_IER)
345
DCMI Masked Interrupt Status Register (DCMI_MIS)
346
DCMI Interrupt Clear Register (DCMI_ICR)
347
DCMI Embedded Synchronization Code Register (DCMI_ESCR)
347
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)
348
DCMI Crop Window Start (DCMI_CWSTRT)
350
DCMI Crop Window Size (DCMI_CWSIZE)
350
DCMI Data Register (DCMI_DR)
351
DCMI Register Map
351
Table 70. DCMI Register Map and Reset Values
351
Advanced-Control Timers (TIM1&TIM8)
353
TIM1&TIM8 Introduction
353
TIM1&TIM8 Main Features
353
Figure 71. Advanced-Control Timer Block Diagram
355
TIM1&TIM8 Functional Description
356
Time-Base Unit
356
Counter Modes
357
Figure 72. Counter Timing Diagram with Prescaler Division Change from 1 to 2
357
Figure 73. Counter Timing Diagram with Prescaler Division Change from 1 to 4
357
Figure 74. Counter Timing Diagram, Internal Clock Divided by 1
358
Figure 75. Counter Timing Diagram, Internal Clock Divided by 2
358
Figure 76. Counter Timing Diagram, Internal Clock Divided by 4
359
Figure 77. Counter Timing Diagram, Internal Clock Divided by N
359
Figure 78. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
359
Figure 79. Counter Timing Diagram, Update Event When ARPE=1
360
Figure 80. Counter Timing Diagram, Internal Clock Divided by 1
361
Figure 81. Counter Timing Diagram, Internal Clock Divided by 2
361
Figure 82. Counter Timing Diagram, Internal Clock Divided by 4
361
Figure 83. Counter Timing Diagram, Internal Clock Divided by N
362
Figure 84. Counter Timing Diagram, Update Event When Repetition Counter
362
Figure 85. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
363
Figure 86. Counter Timing Diagram, Internal Clock Divided by 2
364
Figure 87. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
364
Figure 88. Counter Timing Diagram, Internal Clock Divided by N
364
Repetition Counter
365
Figure 89. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
365
Figure 90. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
365
Figure 91. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
366
Clock Selection
367
Figure 92. Control Circuit in Normal Mode, Internal Clock Divided by 1
367
Figure 93. TI2 External Clock Connection Example
367
Figure 94. Control Circuit in External Clock Mode 1
368
Figure 95. External Trigger Input Block
369
Figure 96. Control Circuit in External Clock Mode 2
369
Capture/Compare Channels
370
Figure 97. Capture/Compare Channel (Example: Channel 1 Input Stage)
370
Figure 98. Capture/Compare Channel 1 Main Circuit
370
Input Capture Mode
371
Figure 99. Output Stage of Capture/Compare Channel (Channel 1 to 3)
371
Figure 100. Output Stage of Capture/Compare Channel (Channel 4)
371
PWM Input Mode
372
Forced Output Mode
373
Figure 101. PWM Input Mode Timing
373
Output Compare Mode
374
PWM Mode
375
Figure 102. Output Compare Mode, Toggle on OC1
375
Figure 103. Edge-Aligned PWM Waveforms (ARR=8)
376
Figure 104. Center-Aligned PWM Waveforms (ARR=8)
377
Complementary Outputs and Dead-Time Insertion
378
Figure 105. Complementary Output with Dead-Time Insertion
378
Figure 106. Dead-Time Waveforms with Delay Greater than the Negative Pulse
378
Using the Break Function
379
Figure 107. Dead-Time Waveforms with Delay Greater than the Positive Pulse
379
Figure 108. Output Behavior in Response to a Break
381
Clearing the Ocxref Signal on an External Event
382
Figure 109. Clearing Timx Ocxref
382
6-Step PWM Generation
383
Figure 110. 6-Step Generation, COM Example (OSSR=1)
383
One-Pulse Mode
384
Figure 111. Example of One Pulse Mode
384
Encoder Interface Mode
385
Table 71. Counting Direction Versus Encoder Signals
386
Figure 112. Example of Counter Operation in Encoder Interface Mode
387
Figure 113. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
387
Timer Input XOR Function
388
Interfacing with Hall Sensors
388
Figure 114. Example of Hall Sensor Interface
389
Timx and External Trigger Synchronization
390
Figure 115. Control Circuit in Reset Mode
390
Figure 116. Control Circuit in Gated Mode
391
Figure 117. Control Circuit in Trigger Mode
392
Timer Synchronization
393
Debug Mode
393
Figure 118. Control Circuit in External Clock Mode 2 + Trigger Mode
393
TIM1&TIM8 Registers
394
TIM1&TIM8 Control Register 1 (Timx_Cr1)
394
TIM1&TIM8 Control Register 2 (Timx_Cr2)
395
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
398
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
400
Table 72. Timx Internal Trigger Connection
400
TIM1&TIM8 Status Register (Timx_Sr)
402
TIM1&TIM8 Event Generation Register (Timx_Egr)
403
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
405
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
408
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
409
Table 73. Output Control Bits for Complementary Ocx and Ocxn Channels with
412
TIM1&TIM8 Counter (Timx_Cnt)
413
TIM1&TIM8 Prescaler (Timx_Psc)
413
TIM1&TIM8 Auto-Reload Register (Timx_Arr)
413
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
414
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)
414
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
415
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)
415
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
416
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)
416
TIM1&TIM8 DMA Control Register (Timx_Dcr)
418
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
419
TIM1&TIM8 Register Map
420
Table 74. TIM1&TIM8 Register Map and Reset Values
420
General-Purpose Timers (TIM2 to TIM5)
422
TIM2 to TIM5 Introduction
422
TIM2 to TIM5 Main Features
422
TIM2 to TIM5 Functional Description
423
Time-Base Unit
423
Figure 119. General-Purpose Timer Block Diagram
423
Figure 120. Counter Timing Diagram with Prescaler Division Change from 1 to 2
424
Counter Modes
425
Figure 121. Counter Timing Diagram with Prescaler Division Change from 1 to 4
425
Figure 122. Counter Timing Diagram, Internal Clock Divided by 1
426
Figure 123. Counter Timing Diagram, Internal Clock Divided by 2
426
Figure 124. Counter Timing Diagram, Internal Clock Divided by 4
426
Figure 125. Counter Timing Diagram, Internal Clock Divided by N
427
Figure 126. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
427
Figure 127. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
428
Figure 128. Counter Timing Diagram, Internal Clock Divided by 1
429
Figure 129. Counter Timing Diagram, Internal Clock Divided by 2
429
Figure 130. Counter Timing Diagram, Internal Clock Divided by 4
429
Figure 131. Counter Timing Diagram, Internal Clock Divided by N
430
Figure 132. Counter Timing Diagram, Update Event
430
Figure 133. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
431
Figure 134. Counter Timing Diagram, Internal Clock Divided by 2
432
Figure 135. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
432
Figure 136. Counter Timing Diagram, Internal Clock Divided by N
432
Figure 137. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
433
Figure 138. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
433
Clock Selection
434
Figure 139. Control Circuit in Normal Mode, Internal Clock Divided by 1
434
Figure 140. TI2 External Clock Connection Example
435
Figure 141. Control Circuit in External Clock Mode 1
435
Capture/Compare Channels
436
Figure 142. External Trigger Input Block
436
Figure 143. Control Circuit in External Clock Mode 2
436
Figure 144. Capture/Compare Channel (Example: Channel 1 Input Stage)
437
Figure 145. Capture/Compare Channel 1 Main Circuit
437
Input Capture Mode
438
Figure 146. Output Stage of Capture/Compare Channel (Channel 1)
438
PWM Input Mode
439
Forced Output Mode
440
Figure 147. PWM Input Mode Timing
440
Output Compare Mode
441
PWM Mode
442
Figure 148. Output Compare Mode, Toggle on OC1
442
Figure 149. Edge-Aligned PWM Waveforms (ARR=8)
443
Figure 150. Center-Aligned PWM Waveforms (ARR=8)
444
One-Pulse Mode
445
Figure 151. Example of One-Pulse Mode
445
Clearing the Ocxref Signal on an External Event
446
Figure 152. Clearing Timx Ocxref
446
Encoder Interface Mode
447
Table 75. Counting Direction Versus Encoder Signals
447
Figure 153. Example of Counter Operation in Encoder Interface Mode
448
Figure 154. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
448
Timer Input XOR Function
449
Timers and External Trigger Synchronization
449
Figure 155. Control Circuit in Reset Mode
450
Figure 156. Control Circuit in Gated Mode
450
Figure 157. Control Circuit in Trigger Mode
451
Figure 158. Control Circuit in External Clock Mode 2 + Trigger Mode
452
Timer Synchronization
453
Figure 159. Master/Slave Timer Example
453
Figure 160. Gating Timer 2 with OC1REF of Timer 1
454
Figure 161. Gating Timer 2 with Enable of Timer 1
455
Figure 162. Triggering Timer 2 with Update of Timer 1
456
Figure 163. Triggering Timer 2 with Enable of Timer 1
456
Debug Mode
458
Figure 164. Triggering Timer 1 and 2 with Timer 1 TI1 Input
458
TIM2 to TIM5 Registers
459
Timx Control Register 1 (Timx_Cr1)
459
Timx Control Register 2 (Timx_Cr2)
461
Timx Slave Mode Control Register (Timx_Smcr)
462
Timx Dma/Interrupt Enable Register (Timx_Dier)
464
Table 76. Timx Internal Trigger Connection
464
Timx Status Register (Timx_Sr)
465
Timx Event Generation Register (Timx_Egr)
467
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
468
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
471
Timx Capture/Compare Enable Register (Timx_Ccer)
472
Table 77. Output Control Bit for Standard Ocx Channels
473
Timx Counter (Timx_Cnt)
474
Timx Prescaler (Timx_Psc)
474
Timx Auto-Reload Register (Timx_Arr)
474
Timx Capture/Compare Register 1 (Timx_Ccr1)
475
Timx Capture/Compare Register 2 (Timx_Ccr2)
475
Timx Capture/Compare Register 3 (Timx_Ccr3)
476
Timx Capture/Compare Register 4 (Timx_Ccr4)
476
Timx DMA Control Register (Timx_Dcr)
477
Timx DMA Address for Full Transfer (Timx_Dmar)
477
TIM2 Option Register (TIM2_OR)
479
TIM5 Option Register (TIM5_OR)
480
Timx Register Map
480
Table 78. TIM2 to TIM5 Register Map and Reset Values
480
General-Purpose Timers (TIM9 to TIM14)
482
TIM9 to TIM14 Introduction
482
TIM9 to TIM14 Main Features
482
TIM9/TIM12 Main Features
482
TIM10/TIM11 and TIM13/TIM14 Main Features
483
Figure 165. General-Purpose Timer Block Diagram (TIM9 and TIM12)
483
Figure 166. General-Purpose Timer Block Diagram (TIM10/11/13/14)
484
TIM9 to TIM14 Functional Description
485
Time-Base Unit
485
Counter Modes
486
Figure 167. Counter Timing Diagram with Prescaler Division Change from 1 to 2
486
Figure 168. Counter Timing Diagram with Prescaler Division Change from 1 to 4
486
Figure 169. Counter Timing Diagram, Internal Clock Divided by 1
487
Figure 170. Counter Timing Diagram, Internal Clock Divided by 2
487
Figure 171. Counter Timing Diagram, Internal Clock Divided by 4
488
Figure 172. Counter Timing Diagram, Internal Clock Divided by N
488
Clock Selection
489
Figure 175. Control Circuit in Normal Mode, Internal Clock Divided by 1
490
Figure 176. TI2 External Clock Connection Example
490
Capture/Compare Channels
491
Figure 177. Control Circuit in External Clock Mode 1
491
Figure 178. Capture/Compare Channel (Example: Channel 1 Input Stage)
491
Input Capture Mode
492
Figure 179. Capture/Compare Channel 1 Main Circuit
492
Figure 180. Output Stage of Capture/Compare Channel (Channel 1)
492
PWM Input Mode (Only for TIM9/12)
493
Forced Output Mode
494
Figure 181. PWM Input Mode Timing
494
Output Compare Mode
495
PWM Mode
496
Figure 182. Output Compare Mode, Toggle on OC1
496
One-Pulse Mode
497
Figure 183. Edge-Aligned PWM Waveforms (ARR=8)
497
Figure 184. Example of One Pulse Mode
497
TIM9/12 External Trigger Synchronization
498
Figure 185. Control Circuit in Reset Mode
499
Figure 186. Control Circuit in Gated Mode
500
Figure 187. Control Circuit in Trigger Mode
500
Timer Synchronization (TIM9/12)
501
Debug Mode
501
TIM9 and TIM12 Registers
502
TIM9/12 Control Register 1 (Timx_Cr1)
502
TIM9/12 Control Register 2 (Timx_Cr2)
503
TIM9/12 Slave Mode Control Register (Timx_Smcr)
504
Table 79. Timx Internal Trigger Connection
505
TIM9/12 Interrupt Enable Register (Timx_Dier)
506
TIM9/12 Status Register (Timx_Sr)
507
TIM9/12 Event Generation Register (Timx_Egr)
508
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
509
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
512
TIM9/12 Counter (Timx_Cnt)
513
TIM9/12 Prescaler (Timx_Psc)
513
TIM9/12 Auto-Reload Register (Timx_Arr)
513
Table 80. Output Control Bit for Standard Ocx Channels
513
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
514
TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)
514
TIM9/12 Register Map
514
Table 81. TIM9/12 Register Map and Reset Values
514
TIM10/11/13/14 Registers
516
TIM10/11/13/14 Control Register 1 (Timx_Cr1)
516
TIM10/11/13/14 Status Register (Timx_Sr)
516
TIM10/11/13/14 Event Generation Register (Timx_Egr)
517
TIM10/11/13/14 Capture/Compare Mode Register 1
519
(Timx_Ccmr1)
519
TIM10/11/13/14 Capture/Compare Enable Register
521
(Timx_Ccer)
521
Table 82. Output Control Bit for Standard Ocx Channels
521
TIM10/11/13/14 Counter (Timx_Cnt)
522
TIM10/11/13/14 Prescaler (Timx_Psc)
522
TIM10/11/13/14 Auto-Reload Register (Timx_Arr)
522
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
523
TIM11 Option Register 1 (TIM11_OR)
523
TIM10/11/13/14 Register Map
524
Table 83. TIM10/11/13/14 Register Map and Reset Values
524
Basic Timers (TIM6&TIM7)
525
TIM6&TIM7 Introduction
525
TIM6&TIM7 Main Features
525
Figure 188. Basic Timer Block Diagram
525
TIM6&TIM7 Functional Description
526
Time-Base Unit
526
Counting Mode
527
Figure 189. Counter Timing Diagram with Prescaler Division Change from 1 to 2
527
Figure 190. Counter Timing Diagram with Prescaler Division Change from 1 to 4
527
Figure 191. Counter Timing Diagram, Internal Clock Divided by 1
528
Figure 192. Counter Timing Diagram, Internal Clock Divided by 2
528
Figure 193. Counter Timing Diagram, Internal Clock Divided by 4
529
Figure 194. Counter Timing Diagram, Internal Clock Divided by N
529
Clock Source
530
Debug Mode
530
TIM6&TIM7 Registers
531
TIM6&TIM7 Control Register 1 (Timx_Cr1)
531
TIM6&TIM7 Control Register 2 (Timx_Cr2)
532
TIM6&TIM7 Dma/Interrupt Enable Register (Timx_Dier)
532
TIM6&TIM7 Status Register (Timx_Sr)
533
TIM6&TIM7 Event Generation Register (Timx_Egr)
533
TIM6&TIM7 Counter (Timx_Cnt)
533
TIM6&TIM7 Prescaler (Timx_Psc)
534
TIM6&TIM7 Auto-Reload Register (Timx_Arr)
534
TIM6&TIM7 Register Map
535
Table 84. TIM6&TIM7 Register Map and Reset Values
535
Independent Watchdog (IWDG)
536
IWDG Introduction
536
IWDG Main Features
536
IWDG Functional Description
536
Hardware Watchdog
536
Register Access Protection
536
Debug Mode
537
IWDG Registers
537
Table 85. Min/Max IWDG Timeout Period at 32 Khz (LSI)
537
Figure 198. Independent Watchdog Block Diagram
537
Key Register (IWDG_KR)
538
Prescaler Register (IWDG_PR)
539
Reload Register (IWDG_RLR)
539
Status Register (IWDG_SR)
540
IWDG Register Map
540
Table 86. IWDG Register Map and Reset Values
540
Window Watchdog (WWDG)
541
WWDG Introduction
541
WWDG Main Features
541
WWDG Functional Description
541
Figure 199. Watchdog Block Diagram
542
How to Program the Watchdog Timeout
543
Figure 200. Window Watchdog Timing Diagram
543
Debug Mode
544
Table 87. Timeout Values at 30 Mhz (F PCLK1 )
544
WWDG Registers
545
Control Register (WWDG_CR)
545
Configuration Register (WWDG_CFR)
546
Status Register (WWDG_SR)
546
WWDG Register Map
547
Table 88. WWDG Register Map and Reset Values
547
Cryptographic Processor (CRYP)
548
CRYP Introduction
548
CRYP Main Features
548
Table 89. Number of Cycles Required to Process each 128-Bit Block (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
548
Table 90. Number of Cycles Required to Process each 128-Bit Block (Stm32F42Xxx and Stm32F43Xxx)
548
CRYP Functional Description
550
Figure 201. Block Diagram (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
550
DES/TDES Cryptographic Core
551
Figure 202. Block Diagram (Stm32F42Xxx and Stm32F43Xxx)
551
Figure 203. DES/TDES-ECB Mode Encryption
553
Figure 204. DES/TDES-ECB Mode Decryption
553
Figure 205. DES/TDES-CBC Mode Encryption
555
AES Cryptographic Core
556
Figure 206. DES/TDES-CBC Mode Decryption
556
Figure 207. AES-ECB Mode Encryption
557
Figure 208. AES-ECB Mode Decryption
558
Figure 209. AES-CBC Mode Encryption
559
Figure 210. AES-CBC Mode Decryption
560
Figure 211. AES-CTR Mode Encryption
561
Figure 212. AES-CTR Mode Decryption
562
Figure 213. Initial Counter Block Structure for the Counter Mode
562
Data Type
567
Table 91. Data Types
568
Initialization Vectors - CRYP_IV0
569
Figure 214. 64-Bit Block Construction According to DATATYPE
569
CRYP Busy State
571
Figure 215. Initialization Vectors Use in the TDES-CBC Encryption
571
Procedure to Perform an Encryption or a Decryption
572
Context Swapping
573
CRYP Interrupts
575
CRYP DMA Interface
575
Figure 216. CRYP Interrupt Mapping Diagram
575
CRYP Registers
576
CRYP Control Register (CRYP_CR) for
576
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
576
CRYP Control Register (CRYP_CR) for
579
Stm32F42Xxx and Stm32F43Xxx
579
CRYP Status Register (CRYP_SR)
581
CRYP Data Input Register (CRYP_DIN)
582
CRYP Data Output Register (CRYP_DOUT)
583
CRYP DMA Control Register (CRYP_DMACR)
584
CRYP Interrupt Mask Set/Clear Register (CRYP_IMSCR)
584
CRYP Raw Interrupt Status Register (CRYP_RISR)
585
CRYP Masked Interrupt Status Register (CRYP_MISR)
585
CRYP Key Registers (CRYP_K0
586
CRYP Initialization Vector Registers (CRYP_IV0
588
CRYP Context Swap Registers (CRYP_CSGCMCCM0
590
CRYP Register Map
591
Table 92. CRYP Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
591
Table 93. CRYP Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
592
Random Number Generator (RNG)
594
RNG Introduction
594
RNG Main Features
594
RNG Functional Description
594
Figure 217. Block Diagram
594
Operation
595
Error Management
595
RNG Registers
595
RNG Control Register (RNG_CR)
596
RNG Status Register (RNG_SR)
596
RNG Data Register (RNG_DR)
597
RNG Register Map
598
Table 94. RNG Register Map and Reset Map
598
Hash Processor (HASH)
599
HASH Introduction
599
HASH Main Features
599
HASH Functional Description
600
Figure 218. Block Diagram for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
600
Figure 219. Block Diagram for Stm32F42Xxx and Stm32F43Xxx
601
Duration of the Processing
602
Data Type
602
Figure 220. Bit, Byte and Half-Word Swapping
603
Message Digest Computing
604
Message Padding
605
Hash Operation
606
HMAC Operation
606
Context Swapping
607
HASH Interrupt
609
HASH Registers
609
HASH Control Register (HASH_CR) for
609
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
609
Figure 221. HASH Interrupt Mapping Diagram
609
HASH Control Register (HASH_CR) for
612
Stm32F42Xxx and Stm32F43Xxx
612
HASH Data Input Register (HASH_DIN)
615
HASH Start Register (HASH_STR)
616
HASH Digest Registers (HASH_HR0
617
HASH Interrupt Enable Register (HASH_IMR)
619
HASH Status Register (HASH_SR)
620
HASH Context Swap Registers (Hash_Csrx)
621
HASH Register Map
622
Table 95. HASH Register Map and Reset Values on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
622
Table 96. HASH Register Map and Reset Values on Stm32F42Xxx and Stm32F43Xxx
623
Real-Time Clock (RTC)
625
Introduction
625
RTC Main Features
626
RTC Functional Description
627
Clock and Prescalers
627
Figure 222. RTC Block Diagram
627
Real-Time Clock and Calendar
628
Programmable Alarms
629
Periodic Auto-Wakeup
629
RTC Initialization and Configuration
630
Reading the Calendar
631
Resetting the RTC
632
RTC Synchronization
633
RTC Reference Clock Detection
633
RTC Coarse Digital Calibration
634
RTC Smooth Digital Calibration
635
Timestamp Function
637
Tamper Detection
638
Calibration Clock Output
639
Alarm Output
640
RTC and Low Power Modes
640
RTC Interrupts
640
Table 97. Effect of Low Power Modes on RTC
640
Table 98. Interrupt Control Bits
641
RTC Registers
642
RTC Time Register (RTC_TR)
642
RTC Date Register (RTC_DR)
643
RTC Control Register (RTC_CR)
644
RTC Initialization and Status Register (RTC_ISR)
646
RTC Prescaler Register (RTC_PRER)
648
RTC Wakeup Timer Register (RTC_WUTR)
649
RTC Calibration Register (RTC_CALIBR)
650
RTC Alarm a Register (RTC_ALRMAR)
651
RTC Alarm B Register (RTC_ALRMBR)
652
RTC Write Protection Register (RTC_WPR)
653
RTC Sub Second Register (RTC_SSR)
653
RTC Shift Control Register (RTC_SHIFTR)
654
RTC Time Stamp Time Register (RTC_TSTR)
655
RTC Time Stamp Date Register (RTC_TSDR)
656
RTC Timestamp Sub Second Register (RTC_TSSSR)
656
RTC Calibration Register (RTC_CALR)
657
RTC Tamper and Alternate Function Configuration Register
658
(Rtc_Tafcr)
658
RTC Alarm a Sub Second Register (RTC_ALRMASSR)
660
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
661
RTC Backup Registers (Rtc_Bkpxr)
662
RTC Register Map
662
Table 99. RTC Register Map and Reset Values
662
Controller Area Network (Bxcan)
664
Bxcan Introduction
664
Bxcan Main Features
664
Bxcan General Description
665
CAN 2.0B Active Core
665
Figure 223. CAN Network Topology
665
Control, Status and Configuration Registers
666
Tx Mailboxes
666
Acceptance Filters
666
Bxcan Operating Modes
667
Figure 224. Dual CAN Block Diagram
667
Initialization Mode
668
Normal Mode
668
Sleep Mode (Low Power)
668
Test Mode
669
Silent Mode
669
Figure 225. Bxcan Operating Modes
669
Loop Back Mode
670
Loop Back Combined with Silent Mode
670
Figure 226. Bxcan in Silent Mode
670
Figure 227. Bxcan in Loop Back Mode
670
Debug Mode
671
Bxcan Functional Description
671
Transmission Handling
671
Figure 228. Bxcan in Combined Mode
671
Time Triggered Communication Mode
673
Reception Handling
673
Figure 230. Receive FIFO States
673
Identifier Filtering
674
Figure 231. Filter Bank Scale Configuration - Register Organization
676
Figure 232. Example of Filter Numbering
677
Message Storage
678
Figure 233. Filtering Mechanism - Example
678
Table 100. Transmit Mailbox Mapping
679
Table 101. Receive Mailbox Mapping
679
Figure 234. CAN Error State Diagram
679
Error Management
680
Bit Timing
680
Figure 235. Bit Timing
681
Figure 236. CAN Frames
682
Bxcan Interrupts
683
Figure 237. Event Flags and Interrupt Generation
683
CAN Registers
684
Register Access Protection
684
CAN Control and Status Registers
684
Figure 229. Transmit Mailbox States
684
CAN Mailbox Registers
694
CAN Filter Registers
701
Bxcan Register Map
705
Table 102. Bxcan Register Map and Reset Values
705
Inter-Integrated Circuit (I 2 C) Interface
708
I 2 C Introduction
708
I 2 C Main Features
708
I 2 C Functional Description
709
Mode Selection
709
Figure 238. I2C Bus Protocol
710
Figure 239. I2C Block Diagram for Stm32F40X/41X
710
I2C Slave Mode
711
Figure 240. I2C Block Diagram for Stm32F42X/43X
711
Figure 241. Transfer Sequence Diagram for Slave Transmitter
713
I2C Master Mode
714
Figure 242. Transfer Sequence Diagram for Slave Receiver
714
Figure 243. Transfer Sequence Diagram for Master Transmitter
716
Figure 244. Transfer Sequence Diagram for Master Receiver
718
Error Conditions
719
Programmable Noise Filter
720
Table 103. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)
720
SDA/SCL Line Control
721
Smbus
721
Table 104. Smbus Vs. I2C
722
DMA Requests
724
Packet Error Checking
725
I 2 C Interrupts
726
Table 105. I2C Interrupt Requests
726
Figure 245. I2C Interrupt Mapping Diagram
727
I 2 C Debug Mode
728
I 2 C Registers
728
I 2 C Control Register 1 (I2C_CR1)
728
I 2 C Control Register 2 (I2C_CR2)
730
I 2 C Own Address Register 1 (I2C_OAR1)
732
I 2 C Own Address Register 2 (I2C_OAR2)
732
I 2 C Data Register (I2C_DR)
733
I 2 C Status Register 1 (I2C_SR1)
733
I 2 C Status Register 2 (I2C_SR2)
737
I 2 C Clock Control Register (I2C_CCR)
738
I 2 C TRISE Register (I2C_TRISE)
739
I 2 C FLTR Register (I2C_FLTR)
740
I2C Register Map
741
Table 106. I2C Register Map and Reset Values
741
Universal Synchronous Asynchronous Receiver Transmitter (USART)
742
USART Introduction
742
USART Main Features
742
USART Functional Description
743
Figure 246. USART Block Diagram
745
USART Character Description
746
Figure 247. Word Length Programming
746
Transmitter
747
Figure 248. Configurable Stop Bits
748
Figure 249. TC/TXE Behavior When Transmitting
749
Receiver
750
Figure 250. Start Bit Detection When Oversampling by 16 or 8
750
Table 107. Noise Detection from Sampled Data
753
Figure 251. Data Sampling When Oversampling by 16
753
Figure 252. Data Sampling When Oversampling by 8
753
Fractional Baud Rate Generation
755
Table 108. Error Calculation for Programmed Baud Rates at F
756
USART Receiver Tolerance to Clock Deviation
764
Multiprocessor Communication
765
Table 118. USART Receiver's Tolerance When DIV Fraction Is 0
765
Table 119. USART Receiver's Tolerance When Div_Fraction Is Different from 0
765
Figure 253. Mute Mode Using Idle Line Detection
766
Figure 254. Mute Mode Using Address Mark Detection
766
Parity Control
767
Table 120. Frame Formats
767
LIN (Local Interconnection Network) Mode
768
Figure 255. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
769
USART Synchronous Mode
770
Figure 256. Break Detection in LIN Mode Vs. Framing Error Detection
770
Figure 257. USART Example of Synchronous Transmission
771
Figure 258. USART Data Clock Timing Diagram (M=0)
771
Single-Wire Half-Duplex Communication
772
Figure 259. USART Data Clock Timing Diagram (M=1)
772
Figure 260. RX Data Setup/Hold Time
772
Smartcard
773
Figure 261. ISO 7816-3 Asynchronous Protocol
773
Figure 262. Parity Error Detection Using the 1.5 Stop Bits
774
Irda SIR ENDEC Block
775
Figure 263. Irda SIR ENDEC- Block Diagram
776
Figure 264. Irda Data Modulation (3/16) -Normal Mode
776
Continuous Communication Using DMA
777
Figure 265. Transmission Using DMA
778
Hardware Flow Control
779
Figure 266. Reception Using DMA
779
Figure 267. Hardware Flow Control between 2 Usarts
779
Figure 268. RTS Flow Control
780
Figure 269. CTS Flow Control
780
USART Interrupts
781
Table 121. USART Interrupt Requests
781
Figure 270. USART Interrupt Mapping Diagram
781
USART Mode Configuration
782
USART Registers
782
Status Register (USART_SR)
782
Table 122. USART Mode Configuration
782
Data Register (USART_DR)
784
Baud Rate Register (USART_BRR)
785
Control Register 1 (USART_CR1)
785
Control Register 2 (USART_CR2)
788
Control Register 3 (USART_CR3)
789
Guard Time and Prescaler Register (USART_GTPR)
792
USART Register Map
793
Table 123. USART Register Map and Reset Values
793
Serial Peripheral Interface (SPI)
794
SPI Introduction
794
SPI and I 2 S Main Features
795
SPI Features
795
I 2 S Features
796
SPI Functional Description
797
General Description
797
Figure 271. SPI Block Diagram
797
Figure 272. Single Master/ Single Slave Application
798
Configuring the SPI in Slave Mode
800
Figure 273. Data Clock Timing Diagram
800
Figure 274. TI Mode - Slave Mode, Single Transfer
802
Figure 275. TI Mode - Slave Mode, Continuous Transfer
802
Configuring the SPI in Master Mode
803
Figure 276. TI Mode - Master Mode, Single Transfer
804
Figure 277. TI Mode - Master Mode, Continuous Transfer
804
Configuring the SPI for Half-Duplex Communication
805
Data Transmission and Reception Procedures
805
Figure 278. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0 and RXONLY=0)
808
Figure 279. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the
808
Figure 280. TXE/BSY Behavior in Master Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the
809
Figure 281. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the Case of
810
Figure 282. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1) in the Case of
811
CRC Calculation
812
Figure 283. TXE/BSY Behavior When Transmitting (BIDIRMODE=0 and RXONLY=0) in the Case of
812
Status Flags
814
Disabling the SPI
815
SPI Communication Using DMA (Direct Memory Addressing)
816
Figure 284. Transmission Using DMA
817
Figure 285. Reception Using DMA
817
Error Flags
818
SPI Interrupts
819
Table 124. SPI Interrupt Requests
819
Figure 286. TI Mode Frame Format Error Detection
819
S Functional Description
820
S General Description
820
Figure 287. I 2 S Block Diagram
820
I2S Full Duplex
821
Figure 288. I2S Full Duplex Block Diagram
821
Supported Audio Protocols
822
Figure 289. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
823
Figure 290. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
823
Figure 291. Transmitting 0X8Eaa33
823
Figure 292. Receiving 0X8Eaa33
824
Figure 293. I 2 S Philips Standard (16-Bit Extended to 32-Bit Packet Frame with CPOL = 0)
824
Figure 294. Example
824
Figure 295. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
825
Figure 296. MSB Justified 24-Bit Frame Length with CPOL = 0
825
Figure 297. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
825
Figure 298. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
826
Figure 299. LSB Justified 24-Bit Frame Length with CPOL = 0
826
Figure 300. Operations Required to Transmit 0X3478Ae
826
Figure 301. Operations Required to Receive 0X3478Ae
827
Figure 302. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
827
Figure 303. Example of LSB Justified 16-Bit Extended to 32-Bit Packet Frame
827
Clock Generator
828
Figure 304. PCM Standard Waveforms (16-Bit)
828
Figure 305. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
828
Figure 306. Audio Sampling Frequency Definition
829
Figure 307. I S Clock Generator Architecture
829
I 2 S Master Mode
830
Table 125. Audio Frequency Precision (for PLLM VCO = 1 Mhz or 2 Mhz)
830
I 2 S Slave Mode
832
Status Flags
834
Error Flags
835
I 2 S Interrupts
836
DMA Features
836
Table 126. I
836
SPI and I 2 S Registers
837
SPI Control Register 1 (SPI_CR1) (Not Used in I 2 S Mode)
837
SPI Control Register 2 (SPI_CR2)
839
SPI Status Register (SPI_SR)
840
SPI Data Register (SPI_DR)
841
SPI CRC Polynomial Register (SPI_CRCPR)
841
Mode)
841
SPI RX CRC Register (SPI_RXCRCR)
842
Mode)
842
SPI TX CRC Register (SPI_TXCRCR)
842
SPI_I 2 S Configuration Register (SPI_I2SCFGR)
843
SPI_I 2 S Prescaler Register (SPI_I2SPR)
844
SPI Register Map
845
Table 127. SPI Register Map and Reset Values
845
Secure Digital Input/Output Interface (SDIO)
846
SDIO Main Features
846
SDIO Bus Topology
846
Figure 308. SDIO "No Response" and "No Data" Operations
847
Figure 309. SDIO (Multiple) Block Read Operation
847
Figure 310. SDIO (Multiple) Block Write Operation
848
Figure 311. SDIO Sequential Read Operation
848
Figure 312. SDIO Sequential Write Operation
848
SDIO Functional Description
849
Figure 313. SDIO Block Diagram
849
SDIO Adapter
850
Table 128. SDIO I/O Definitions
850
Figure 314. SDIO Adapter
850
Figure 315. Control Unit
851
Figure 316. SDIO Adapter Command Path
852
Figure 317. Command Path State Machine (CPSM)
853
Table 129. Command Format
854
Figure 318. SDIO Command Transfer
854
Table 130. Short Response Format
855
Table 131. Long Response Format
855
Table 132. Command Path Status Flags
855
Figure 319. Data Path
856
Figure 320. Data Path State Machine (DPSM)
857
Table 133. Data Token Format
858
Table 134. Transmit FIFO Status Flags
859
SDIO APB2 Interface
860
Table 135. Receive FIFO Status Flags
860
Card Functional Description
861
Card Identification Mode
861
Card Reset
861
Operating Voltage Range Validation
861
Card Identification Process
862
Block Write
863
Block Read
863
Stream Access, Stream Write and Stream Read (Multimediacard Only)
864
Erase: Group Erase and Sector Erase
865
Wide Bus Selection or Deselection
866
Protection Management
866
Card Status Register
869
Table 136. Card Status
870
SD Status Register
872
Table 137. SD Status
872
Table 138. Speed Class Code Field
874
Table 139. Performance Move Field
874
Table 140. AU_SIZE Field
875
Table 141. Maximum au Size
875
Table 142. Erase Size Field
875
Table 143. Erase Timeout Field
875
SD I/O Mode
876
Table 144. Erase Offset Field
876
Commands and Responses
877
Table 145. Block-Oriented Write Commands
878
Table 146. Block-Oriented Write Protection Commands
879
Table 147. Erase Commands
879
Table 148. I/O Mode Commands
879
Response Formats
880
Table 149. Lock Card
880
Table 150. Application-Specific Commands
880
R1 (Normal Response Command)
881
R1B
881
R2 (CID, CSD Register)
881
Table 151. R1 Response
881
Table 152. R2 Response
881
R3 (OCR Register)
882
R4 (Fast I/O)
882
R4B
882
Table 153. R3 Response
882
Table 154. R4 Response
882
Table 155. R4B Response
882
R5 (Interrupt Request)
883
Table 156. R5 Response
883
SDIO I/O Card-Specific Operations
884
SDIO I/O Read Wait Operation by SDIO_D2 Signalling
884
Table 157. R6 Response
884
SDIO Read Wait Operation by Stopping SDIO_CK
885
SDIO Suspend/Resume Operation
885
SDIO Interrupts
885
CE-ATA Specific Operations
885
Command Completion Signal Disable
885
Command Completion Signal Enable
886
CE-ATA Interrupt
886
Aborting CMD61
886
HW Flow Control
886
SDIO Registers
887
SDIO Power Control Register (SDIO_POWER)
887
SDI Clock Control Register (SDIO_CLKCR)
887
SDIO Argument Register (SDIO_ARG)
889
SDIO Command Register (SDIO_CMD)
890
SDIO Command Response Register (SDIO_RESPCMD)
891
SDIO Response 1
891
Table 158. Response Type and Sdio_Respx Registers
891
SDIO Data Timer Register (SDIO_DTIMER)
892
SDIO Data Length Register (SDIO_DLEN)
892
SDIO Data Control Register (SDIO_DCTRL)
893
SDIO Data Counter Register (SDIO_DCOUNT)
894
SDIO Status Register (SDIO_STA)
895
SDIO Interrupt Clear Register (SDIO_ICR)
896
SDIO Mask Register (SDIO_MASK)
898
SDIO FIFO Counter Register (SDIO_FIFOCNT)
900
SDIO Data FIFO Register (SDIO_FIFO)
901
SDIO Register Map
901
Table 159. SDIO Register Map
901
Ethernet (ETH): Media Access Control (MAC) with DMA Controller
903
Ethernet Introduction
903
Ethernet Main Features
903
MAC Core Features
904
DMA Features
905
PTP Features
905
Ethernet Pins
906
Table 160. Alternate Function Mapping
906
Ethernet Functional Description: SMI, MII and RMII
907
Station Management Interface: SMI
907
Figure 321. ETH Block Diagram
907
Table 161. Management Frame Format
908
Figure 322. SMI Interface Signals
908
Figure 323. MDIO Timing and Frame Structure - Write Cycle
909
Figure 324. MDIO Timing and Frame Structure - Read Cycle
909
Media-Independent Interface: MII
910
Table 162. Clock Range
910
Figure 325. Media Independent Interface Signals
910
Table 163. TX Interface Signal Encoding
911
Table 164. RX Interface Signal Encoding
911
Reduced Media-Independent Interface: RMII
912
Figure 326. MII Clock Sources
912
MII/RMII Selection
913
Figure 327. Reduced Media-Independent Interface Signals
913
Figure 328. RMII Clock Sources
913
Ethernet Functional Description: MAC 802.3
914
Figure 329. Clock Scheme
914
MAC 802.3 Frame Format
915
Figure 330. Address Field Format
916
Figure 331. MAC Frame Format
917
MAC Frame Transmission
918
Figure 332. Tagged MAC Frame Format
918
Figure 333. Transmission Bit Order
924
Figure 334. Transmission with no Collision
924
MAC Frame Reception
925
Figure 335. Transmission with Collision
925
Figure 336. Frame Transmission in MMI and RMII Modes
925
Table 165. Frame Statuses
927
Figure 337. Receive Bit Order
929
MAC Interrupts
930
Figure 338. Reception with no Error
930
Figure 339. Reception with Errors
930
Figure 340. Reception with False Carrier Indication
930
MAC Filtering
931
Figure 341. MAC Core Interrupt Masking Scheme
931
Table 166. Destination Address Filtering
933
MAC Loopback Mode
934
MAC Management Counters: MMC
934
Table 167. Source Address Filtering
934
Power Management: PMT
935
Figure 342. Wakeup Frame Filter Register
936
Precision Time Protocol (IEEE1588 PTP)
938
Figure 343. Networked Time Synchronization
939
Figure 344. System Time Update Using the Fine Correction Method
941
Figure 345. PTP Trigger Output to TIM2 ITR1 Connection
943
Ethernet Functional Description: DMA Controller Operation
944
Figure 346. PPS Output
944
Initialization of a Transfer Using DMA
945
Host Bus Burst Access
945
Figure 347. Descriptor Ring and Chain Structure
945
Host Data Buffer Alignment
946
Buffer Size Calculations
946
DMA Arbiter
947
Error Response to DMA
947
Tx DMA Configuration
947
Figure 348. Txdma Operation in Default Mode
949
Figure 349. Txdma Operation in OSF Mode
951
Figure 350. Normal Transmit Descriptor
952
Figure 351. Enhanced Transmit Descriptor
957
Rx DMA Configuration
958
Figure 352. Receive DMA Operation
959
Figure 353. Normal Rx DMA Descriptor Structure
961
Table 168. Receive Descriptor 0 - Encoding for Bits 7, 5 and
963
Figure 354. Enhanced Receive Descriptor Field Format with IEEE1588 Time Stamp Enabled
968
DMA Interrupts
970
Ethernet Interrupts
971
Figure 355. Interrupt Scheme
971
Ethernet Register Descriptions
972
MAC Register Description
972
Figure 356. Ethernet MAC Remote Wakeup Frame Filter Register (ETH_MACRWUFFR)
981
MMC Register Description
991
IEEE 1588 Time Stamp Registers
996
DMA Register Description
1003
Ethernet Register Maps
1017
Table 170. Ethernet Register Map and Reset Values
1017
USB On-The-Go Full-Speed (OTG_FS)
1021
OTG_FS Introduction
1021
OTG_FS Main Features
1022
General Features
1022
Host-Mode Features
1023
Peripheral-Mode Features
1023
OTG_FS Functional Description
1024
OTG Full-Speed Core
1024
Figure 357. Block Diagram
1024
Full-Speed OTG PHY
1025
OTG Dual Role Device (DRD)
1026
ID Line Detection
1026
HNP Dual Role Device
1026
Figure 358. OTG A-B Device Connection
1026
SRP Dual Role Device
1027
USB Peripheral
1027
SRP-Capable Peripheral
1028
Peripheral States
1028
Figure 359. USB Peripheral-Only Connection
1028
Peripheral Endpoints
1029
USB Host
1031
SRP-Capable Host
1032
USB Host States
1032
Figure 360. USB Host-Only Connection
1032
Host Channels
1034
Host Scheduler
1035
SOF Trigger
1036
Host Sofs
1036
Figure 361. SOF Connectivity
1036
Peripheral Sofs
1037
Power Options
1037
Dynamic Update of the OTG_FS_HFIR Register
1038
Figure 362. Updating OTG_FS_HFIR Dynamically
1038
USB Data Fifos
1039
Peripheral FIFO Architecture
1039
Peripheral Rx FIFO
1039
Figure 363. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1039
Peripheral Tx Fifos
1040
Host FIFO Architecture
1040
Host Rx FIFO
1040
Figure 364. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1040
Host Tx Fifos
1041
FIFO RAM Allocation
1041
Device Mode
1041
Host Mode
1042
USB System Performance
1042
OTG_FS Interrupts
1043
OTG_FS Control and Status Registers
1044
Figure 365. Interrupt Hierarchy
1044
CSR Memory Map
1045
Table 171. Core Global Control and Status Registers (Csrs)
1046
Figure 366. CSR Memory Map
1046
Table 172. Host-Mode Control and Status Registers (Csrs)
1047
Table 173. Device-Mode Control and Status Registers
1048
OTG_FS Global Registers
1050
Table 174. Data FIFO (DFIFO) Access Register Map
1050
Table 175. Power and Clock Gating Control and Status Registers
1050
Host-Mode Registers
1072
Device-Mode Registers
1083
Table 176. Minimum Duration for Soft Disconnect
1085
OTG_FS Power and Clock Gating Control Register
1105
(Otg_Fs_Pcgcctl)
1105
OTG_FS Register Map
1106
Table 177. OTG_FS Register Map and Reset Values
1106
OTG_FS Programming Model
1113
Core Initialization
1113
Host Initialization
1114
Device Initialization
1114
Host Programming Model
1115
Figure 367. Transmit FIFO Write Task
1116
Figure 368. Receive FIFO Read Task
1117
Figure 369. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions
1119
Figure 370. Bulk/Control in Transactions
1122
Figure 371. Normal Interrupt OUT/IN Transactions
1124
Figure 372. Normal Isochronous OUT/IN Transactions
1129
Device Programming Model
1132
Operational Model
1134
Figure 373. Receive FIFO Packet Read
1135
Figure 374. Processing a SETUP Packet
1137
Figure 375. Bulk out Transaction
1143
Worst Case Response Time
1151
OTG Programming Model
1152
Figure 376. TRDT Max Timing Case
1152
Figure 377. A-Device SRP
1153
Figure 378. B-Device SRP
1154
Figure 379. A-Device HNP
1155
Figure 380. B-Device HNP
1157
USB On-The-Go High-Speed (OTG_HS)
1159
OTG_HS Introduction
1159
OTG_HS Main Features
1160
General Features
1160
Host-Mode Features
1161
Peripheral-Mode Features
1161
OTG_HS Functional Description
1162
High-Speed OTG PHY
1162
External Full-Speed OTG PHY Using the I2C Interface
1162
Embedded Full-Speed OTG PHY
1162
Figure 381. USB OTG Interface Block Diagram
1162
OTG Dual-Role Device
1163
ID Line Detection
1163
HNP Dual Role Device
1163
SRP Dual-Role Device
1163
USB Functional Description in Peripheral Mode
1164
SRP-Capable Peripheral
1164
Peripheral States
1164
Peripheral Endpoints
1165
USB Functional Description on Host Mode
1168
SRP-Capable Host
1168
USB Host States
1168
Host Channels
1170
Host Scheduler
1171
SOF Trigger
1172
Host Sofs
1172
Peripheral Sofs
1173
USB_HS Power Modes
1174
Dynamic Update of the OTG_HS_HFIR Register
1174
FIFO RAM Allocation
1175
Peripheral Mode
1175
Host Mode
1175
Figure 382. Updating OTG_HS_HFIR Dynamically
1175
OTG_HS Interrupts
1176
OTG_HS Control and Status Registers
1177
Figure 383. Interrupt Hierarchy
1177
CSR Memory Map
1179
Table 178. Core Global Control and Status Registers (Csrs)
1179
Figure 384. CSR Memory Map
1179
Table 179. Host-Mode Control and Status Registers (Csrs)
1180
Table 180. Device-Mode Control and Status Registers
1181
Table 181. Data FIFO (DFIFO) Access Register Map
1183
Table 182. Power and Clock Gating Control and Status Registers
1183
OTG_HS Global Registers
1184
Host-Mode Registers
1208
Device-Mode Registers
1220
Table 183. Minimum Duration for Soft Disconnect
1223
OTG_HS Power and Clock Gating Control Register
1247
(Otg_Hs_Pcgcctl)
1247
OTG_HS Register Map
1248
Table 184. OTG_HS Register Map and Reset Values
1248
OTG_HS Programming Model
1260
Core Initialization
1260
Host Initialization
1261
Device Initialization
1262
DMA Mode
1262
Host Programming Model
1262
Figure 385. Transmit FIFO Write Task
1265
Figure 386. Receive FIFO Read Task
1266
Figure 387. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - DMA
1268
Mode
1268
Figure 388. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - Slave
1269
Figure 389. Bulk/Control in Transactions - DMA Mode
1272
Figure 390. Bulk/Control in Transactions - Slave Mode
1273
Figure 391. Normal Interrupt OUT/IN Transactions - DMA Mode
1275
Figure 392. Normal Interrupt OUT/IN Transactions - Slave Mode
1276
Figure 393. Normal Isochronous OUT/IN Transactions - DMA Mode
1281
Figure 394. Normal Isochronous OUT/IN Transactions - Slave Mode
1282
Device Programming Model
1290
Operational Model
1292
Figure 395. Receive FIFO Packet Read in Slave Mode
1293
Figure 396. Processing a SETUP Packet
1295
Figure 397. Slave Mode Bulk out Transaction
1301
Worst Case Response Time
1309
OTG Programming Model
1310
Figure 398. TRDT Max Timing Case
1310
Figure 399. A-Device SRP
1311
Figure 400. B-Device SRP
1312
Figure 401. A-Device HNP
1313
Figure 402. B-Device HNP
1315
Flexible Static Memory Controller (FSMC)
1317
FSMC Main Features
1317
Block Diagram
1318
Figure 403. FSMC Block Diagram
1318
AHB Interface
1319
Supported Memories and Transactions
1319
External Device Address Mapping
1320
NOR/PSRAM Address Mapping
1320
Figure 404. FSMC Memory Banks
1320
NAND/PC Card Address Mapping
1321
Table 185. NOR/PSRAM Bank Selection
1321
Table 186. External Memory Address
1321
Table 187. Memory Mapping and Timing Registers
1321
NOR Flash/Psram Controller
1322
Table 188. NAND Bank Selections
1322
External Memory Interface Signals
1323
Table 189. Programmable NOR/PSRAM Access Parameters
1323
Table 190. Nonmultipled I/O nor Flash
1323
Table 191. Multiplexed I/O nor Flash
1324
Table 192. Nonmultiplexed I/Os PSRAM/SRAM
1324
Supported Memories and Transactions
1325
Table 193. Multiplexed I/O PSRAM
1325
Table 194. nor Flash/Psram Controller: Example of Supported Memories
1325
General Timing Rules
1326
NOR Flash/Psram Controller Asynchronous Transactions
1327
Figure 405. Mode1 Read Accesses
1327
Table 195. Fsmc_Bcrx Bit Fields
1328
Figure 406. Mode1 Write Accesses
1328
Table 196. Fsmc_Btrx Bit Fields
1329
Figure 407. Modea Read Accesses
1330
Figure 408. Modea Write Accesses
1330
Table 197. Fsmc_Bcrx Bit Fields
1331
Table 198. Fsmc_Btrx Bit Fields
1331
Table 199. Fsmc_Bwtrx Bit Fields
1332
Figure 409. Mode2 and Mode B Read Accesses
1332
Figure 410. Mode2 Write Accesses
1333
Figure 411. Modeb Write Accesses
1333
Table 200. Fsmc_Bcrx Bit Fields
1334
Table 201. Fsmc_Btrx Bit Fields
1334
Table 202. Fsmc_Bwtrx Bit Fields
1335
Figure 412. Mode C Read Accesses
1335
Table 203. Fsmc_Bcrx Bit Fields
1336
Figure 413. Mode C Write Accesses
1336
Table 204. Fsmc_Btrx Bit Fields
1337
Table 205. Fsmc_Bwtrx Bit Fields
1337
Figure 414. Mode D Read Accesses
1338
Figure 415. Mode D Write Accesses
1338
Table 206. Fsmc_Bcrx Bit Fields
1339
Table 207. Fsmc_Btrx Bit Fields
1339
Table 208. Fsmc_Bwtrx Bit Fields
1340
Figure 416. Multiplexed Read Accesses
1340
Table 209. Fsmc_Bcrx Bit Fields
1341
Figure 417. Multiplexed Write Accesses
1341
Table 210. Fsmc_Btrx Bit Fields
1342
Figure 418. Asynchronous Wait During a Read Access
1343
Synchronous Burst Transactions
1345
Table 211. Fsmc_Bcrx Bit Fields
1347
Figure 421. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)
1347
Table 212. Fsmc_Btrx Bit Fields
1348
Table 213. Fsmc_Bcrx Bit Fields
1349
Figure 422. Synchronous Multiplexed Write Mode - PSRAM (CRAM)
1349
Table 214. Fsmc_Btrx Bit Fields
1350
NOR/PSRAM Control Registers
1351
NAND Flash/Pc Card Controller
1357
External Memory Interface Signals
1358
Table 215. Programmable NAND/PC Card Access Parameters
1358
Table 216. 8-Bit NAND Flash
1358
Table 217. 16-Bit NAND Flash
1359
Table 218. 16-Bit PC Card
1359
NAND Flash / PC Card Supported Memories and Transactions
1360
Timing Diagrams for NAND and PC Card
1360
Table 219. Supported Memories and Transactions
1360
NAND Flash Operations
1361
Figure 423. NAND/PC Card Controller Timing for Common Memory Access
1361
NAND Flash Pre-Wait Functionality
1362
Figure 424. Access to Non 'CE Don't Care' NAND-Flash
1362
Error Correction Code Computation ECC (NAND Flash)
1363
PC Card/Compactflash Operations
1363
Table 220. 16-Bit PC-Card Signals and Access Type
1364
NAND Flash/Pc Card Control Registers
1366
Table 221. ECC Result Relevant Bits
1372
FSMC Register Map
1373
Table 222. FSMC Register Map
1373
Debug Support (DBG)
1375
Overview
1375
Figure 425. Block Diagram of STM32 MCU and Cortex™-M4F-Level Debug Support
1375
Reference ARM Documentation
1376
SWJ Debug Port (Serial Wire and JTAG)
1376
Mechanism to Select the JTAG-DP or the SW-DP
1377
Pinout and Debug Port Pins
1377
Figure 426. SWJ Debug Port
1377
SWJ Debug Port Pins
1378
Flexible SWJ-DP Pin Assignment
1378
Table 223. SWJ Debug Port Pins
1378
Table 224. Flexible SWJ-DP Pin Assignment
1378
Internal Pull-Up and Pull-Down on JTAG Pins
1379
Using Serial Wire and Releasing the Unused Debug Pins as Gpios
1380
Stm32F4Xx JTAG TAP Connection
1380
Figure 427. JTAG TAP Connections
1381
ID Codes and Locking Mechanism
1382
MCU Device ID Code
1382
Boundary Scan TAP
1382
Cortex™-M4F TAP
1382
Cortex™-M4F JEDEC-106 ID Code
1383
JTAG Debug Port
1383
Table 225. JTAG Debug Port Data Registers
1383
SW Debug Port
1385
SW Protocol Introduction
1385
SW Protocol Sequence
1385
Table 226. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1385
SW-DP State Machine (Reset, Idle States, ID Code)
1386
Table 227. Packet Request (8-Bits)
1386
Table 228. ACK Response (3 Bits)
1386
Table 229. DATA Transfer (33 Bits)
1386
DP and AP Read/Write Accesses
1387
SW-DP Registers
1387
Table 230. SW-DP Registers
1387
SW-AP Registers
1388
AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP
1389
Table 231. Cortex™-M4F AHB-AP Registers
1389
Core Debug
1390
Table 232. Core Debug Registers
1390
Capability of the Debugger Host to Connect under System Reset
1391
FPB (Flash Patch Breakpoint)
1391
DWT (Data Watchpoint Trigger)
1392
ITM (Instrumentation Trace Macrocell)
1392
General Description
1392
Time Stamp Packets, Synchronization and Overflow Packets
1392
Table 233. Main ITM Registers
1393
ETM (Embedded Trace Macrocell)
1394
General Description
1394
Signal Protocol, Packet Types
1394
Main ETM Registers
1395
Configuration Example
1395
MCU Debug Component (DBGMCU)
1395
Debug Support for Low-Power Modes
1395
Table 234. Main ETM Registers
1395
Debug Support for Timers, Watchdog, Bxcan and I
1396
1396
1396
Debug MCU Configuration Register
1396
Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)
1398
Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)
1399
TPIU (Trace Port Interface Unit)
1400
Introduction
1400
Figure 428. TPIU Block Diagram
1400
TRACE Pin Assignment
1401
Table 235. Asynchronous TRACE Pin Assignment
1401
Table 236. Synchronous TRACE Pin Assignment
1401
TPUI Formatter
1402
Table 237. Flexible TRACE Pin Assignment
1402
TPUI Frame Synchronization Packets
1403
Transmission of the Synchronization Frame Packet
1403
Synchronous Mode
1403
Asynchronous Mode
1404
TRACECLKIN Connection Inside the Stm32F4Xx
1404
TPIU Registers
1405
Table 238. Important TPIU Registers
1405
33.17.10 Example of Configuration
1406
DBG Register Map
1406
Table 239. DBG Register Map and Reset Values
1406
Device Electronic Signature
1407
Unique Device ID Register (96 Bits)
1407
Flash Size
1408
Revision History
1413
Table 240. Document Revision History
1413
Figure 419. Asynchronous Wait During a Write Access
1421
Figure 420. Wait Configurations
1421
4
Based on 1 rating
Ask a question
Give review
Questions and Answers:
Need help?
Do you have a question about the ST STM32F40 Series and is the answer not in the manual?
Ask a question
ST STM32F40 Series Specifications
General
Brand
ST
Model
STM32F40 Series
Category
Microcontrollers
Language
English
Related product manuals
ST STM32F412
1163 pages
ST STM32F446 Series
1328 pages
ST STM32F2
1371 pages
ST STM32F205
29 pages
ST STM32F072
27 pages
ST STM32F030
40 pages
ST STM32F101xx
1096 pages
ST STM32F0 Series
91 pages
ST STM32F7 Series
54 pages
ST STM32F10 Series
519 pages
ST STM32F207 series
1381 pages
ST STM32F103 series
14 pages
To Next PageTo Next PageTo Previous PageTo Previous Page
Need help?
General
