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ST STM32F40 Series

ST STM32F40 Series
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Hash processor (HASH) RM0090
603/1422 Doc ID 018909 Rev 4
Figure 220. Bit, byte and half-word swapping
B y t e 3B y t e 2B y t e 1B y t e 0
bi
t s 7 . . . 0b i t s 7 .. . 0
b
i t s 7 .. . 0bi t s 7 . . . 0
H
A
S
H_D
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N
bit string organization in
bi t 0 bi t 1 bi t 2 9 b i t 3 0 b i t 3 1
Bit
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B y t e 0B y t e 1B y t e 2B y t e 3
bi
t s 7 . . . 0b i t s 7 .. . 0
b i t s 7 .. . 0bi t s 7 . . . 0
HA
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0
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Half-wo r d 0
bi
t s 15 . . . 0
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A
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A
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D
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D
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Half-wo r d 1
bi
t s 15 . . . 0
Half-wor d 0
bi
t s 15 .. . 0
Half-wor
d 1
bi
t s 15 .. . 0
“1”
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ad
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ing is perfo
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ed
on this side of the
bit
s
t
ri
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g.
ai16082
Hash processor: Big-Endian
Bits entred with little-Endian format
A-In case of binary data hash, all bits should be swapped as below
B-In case of byte data hash, all bytes should be swapped as below
C-In case of half-word hash, all half-word should be swapped as below
Bytes entred with little-Endian format
Bit string organization in
Hash processor: Big-Endian
half word entred with little-Endian format
Bit string organization in
Hash processor: Big-Endian

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