ST STM32F40 Series User Manual

RM0090 Embedded Flash memory interface
Doc ID 018909 Rev 4 62/1422
Note: On STM32F405xx/07xx and STM32F415xx/17xx devices:
- when VOS = '0', the maximum value of f
HCLK
= 144 MHz.
- when VOS = '1', the maximum value of f
HCLK
= 168 MHz.
On STM32F42xxx and STM32F43xxx devices:
- when VOS[1:0] = '0x01', the maximum value of f
HCLK
is 120 MHz.
- when VOS[1:0] = '0x10', the maximum value of f
HCLK
is 144 MHz.
- when VOS[1:0] = '0x11', the maximum value of f
HCLK
is 168 MHz
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states needed to access the Flash memory with the CPU frequency.
Increasing the CPU frequency
1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR
register
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Table 7. Number of wait states according to CPU clock (HCLK) frequency
Wait states (WS)
(LATENCY)
HCLK (MHz)
Voltag e range
2.7 V - 3.6 V
Voltag e range
2.4 V - 2.7 V
Voltage rang e
2.1 V - 2.4 V
Voltag e range
1.8 V - 2.1 V
Prefetch OFF
0 WS (1 CPU cycle) 0 < HCLK≤ 30 0 < HCLK ≤ 24 0 < HCLK ≤ 22 0 < HCLK ≤ 20
1 WS (2 CPU cycles) 30 < HCLK ≤ 60 24 < HCLK≤ 48 22 < HCLK ≤ 44 20 <HCLK ≤ 40
2 WS (3 CPU cycles) 60 < HCLK ≤ 90 48 < HCLK≤ 72 44 < HCLK≤ 66 40 < HCLK≤ 60
3 WS (4 CPU cycles) 90 < HCLK ≤ 120 72 < HCLK≤ 96 66 < HCLK ≤ 88 60 < HCLK≤ 80
4 WS (5 CPU cycles) 120 < HCLK ≤ 150 96 < HCLK≤ 120 88 < HCLK≤ 110 80 < HCLK≤ 100
5 WS (6 CPU cycles) 150 < HCLK ≤ 168 120 < HCLK ≤ 144 110 < HCLK≤ 132 100 < HCLK≤ 120
6 WS (7 CPU cycles)
144 < HCLK ≤ 168 132 < HCLK≤ 154 120 < HCLK≤ 140
7 WS (8 CPU cycles)
154 < HCLK ≤ 168 140 < HCLK≤ 160

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English