Memory and bus architecture RM0090
51/1422 Doc ID 018909 Rev 4
2.1.1 S0: I-bus
This bus connects the Instruction bus of the Cortex™-M4F core to the BusMatrix. This bus
is used by the core to fetch instructions. The target of this bus is a memory containing code
(internal Flash memory/SRAM or external memories through the FSMC).
2.1.2 S1: D-bus
This bus connects the databus of the Cortex™-M4F and the 64-Kbyte CCM data RAM to the
BusMatrix. This bus is used by the core for literal load and debug access. The target of this
bus is a memory containing code or data (internal Flash memory or external memories
through the FSMC).
2.1.3 S2: S-bus
This bus connects the system bus of the Cortex™-M4F core to a BusMatrix. This bus is
used to access data located in a peripheral or in SRAM. Instructions may also be fetch on
this bus (less efficient than ICode). The targets of this bus are the 112, 64, and 16 Kbytes
internal SRAMs, the AHB1 peripherals including the APB peripherals, the AHB2 peripherals
and the external memories through the FSMC.
2.1.4 S3, S4: DMA memory bus
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal SRAMs (112, 64, and 16 Kbytes) and external memories through the FSMC.
2.1.5 S5: DMA peripheral bus
This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is
used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.
The targets of this bus are the AHB and APB peripherals plus data memories: internal
SRAM and external memories through the FSMC.
2.1.6 S6: Ethernet DMA bus
This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by
the Ethernet DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAMs (112, 64, and 16 Kbytes) and external memories through the
FSMC.
2.1.7 S7: USB OTG HS DMA bus
This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is
used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAMs (112, 64, and 16 Kbytes) and external memories through the
FSMC.
2.1.8 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
round-robin algorithm.
To Next Page
Loading...
Need help?
General
