RM0090 Digital camera interface (DCMI)
Doc ID 018909 Rev 4 332/1422
13.5.1 DMA interface
The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA
request is generated each time the camera interface receives a complete 32-bit data block
in its register.
13.5.2 DCMI physical interface
The interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported.
The camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the
EDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused input pins
must be connected to ground.
The data are synchronous with PIXCLK and change on the rising/falling edge of the pixel
clock depending on the polarity.
The HSYNC signal indicates the start/end of a line.
The VSYNC signal indicates the start/end of a frame
Figure 64. DCMI signal waveforms
1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and
DCMI_VSYNC is 1.
1. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.
Table 61. DCMI signals
Signal name Signal description
8 bits
10 bits
12 bits
14 bits
D[0..7]
D[0..9]
D[0..11]
D[0..13]
Data
PIXCLK Pixel clock
HSYNC Horizontal synchronization / Data valid
VSYNC Vertical synchronization
DCMI_PIXCLK
DCMI_DR[0:13]
DCMI_HSYNC
DCMI_VSYNC
ai15606b
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