ST STM32F40 Series User Manual

Cryptographic processor (CRYP) RM0090
571/1422 Doc ID 018909 Rev 4
Figure 215. Initialization vectors use in the TDES-CBC encryption
20.3.5 CRYP busy state
When there is enough data in the input FIFO (at least 2 words for the DES or TDES
algorithm mode, 4 words for the AES algorithm mode) and enough free-space in the output
FIFO (at least 2 (DES/TDES) or 4 (AES) word locations), and when the bit CRYPEN = 1 in
the CRYP_CR register, then the cryptographic processor automatically starts an encryption
or decryption process (according to the value of the ALGODIR bit in the CRYP_CR register).
This process takes 48 AHB2 clock cycles for the Triple-DES algorithm, 16 AHB2 clock
cycles for the simple DES algorithm, and 14, 16 or 18 AHB2 clock cycles for the AES with
key lengths of 128, 192 or 256 bits, respectively. During the whole process, the BUSY bit in
the CRYP_SR register is set to ‘1’. At the end of the process, two (DES/TDES) or four (AES)
words are written by the CRYP Core into the output FIFO, and the BUSY bit is cleared. In
the CBC, CTR mode, the initialization vectors CRYP_IVx(L/R)R (x = 0..3) are updated as
well.
CRYP_IVL
bit string
M1 M2 M30 M31 M32
TDES-CBC encryption example, DATATYPE = 11b
M33 M34 M62 M63 M64
bit 0
bit 1bit 2bit 30bit 31
bit 0bit 1bit 2bit 30bit 31
first word written into the CRYP_DIN register
second word written into the CRYP_DIN register
IV1
CRYP_IVR
0123031 0123031
DEA Encrypt, K1
DEA Decrypt, K2
DEA Encrypt, K3
CRYP_IVL CRYP_IVR
0123031 0123031
CRYP result is copied
back to the CRYP_IVL/R
registers after cyphering
OUT FIFO
First word from the OUT FIFO contains the left part of the cyphertext block (O1...32)
Second word from OUT FIFO contains the right part of cyphertext block (O33...64)
IV2 IV30 IV31 IV32 IV33 IV34 IV62 IV63 IV64
I1
I2 I30 I33 I34 I62 I63 I64I31 I32
IV1
IV2 IV30 IV31 IV32 IV33 IV34 IV62 IV63 IV64
ai16076

ST STM32F40 Series Specifications

General

Brand	ST
Model	STM32F40 Series
Category	Microcontrollers
Language	English