General-purpose timers (TIM9 to TIM14) RM0090
487/1422 Doc ID 018909 Rev 4
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
● The auto-reload shadow register is updated with the preload value (TIMx_ARR),
● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Figure 169. Counter timing diagram, internal clock divided by 1
Figure 170. Counter timing diagram, internal clock divided by 2
CK_PSC
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 0732 33 34 35 3631
CK_PSC
0035 0000 0001 0002 0003
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0034
0036
Counter overflow
Update event (UEV)
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