RM0090 Serial peripheral interface (SPI)
Doc ID 018909 Rev 4 804/1422
SPI TI protocol in master mode
In master mode, the SPI interface is compatible with the TI protocol. The FRF bit of the
SPI_CR2 register can be used to configure the master SPI serial communications to be
compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever
the values set in the SPI_CR1 register. NSS management is also specific to the TI protocol
which makes the configuration of NSS management through the SPI_CR1 and SPI_CR2
registers (SSM, SSI, SSOE) transparent for the user.
Figure 276: TI mode - master mode, single transfer and Figure 277: TI mode - master mode,
continuous transfer) show the SPI master communication waveforms when the TI mode is
selected in master mode.
Figure 276. TI mode - master mode, single transfer
Figure 277. TI mode - master mode, continuous transfer
ai18436
MSBIN
MOSI
input
NSS
output
SCK
output
trigger
edge
sampling
edge
trigger
edge
sampling
edge
trigger
edge
sampling
edge
DONTCARE LSBIN DONTCARE
MISO
output
1 or 0 MSBOUT
LSBOUT
ai18437
MSBOUT
MOSI
output
NSS
output
SCK
output
trigger sampling trigger sampling trigger sampling
DONTCARE LSBOUT
DONTCARE
MISO
intput
1 or 0 MSBIN
LSBIN
MSBOUT LSBOUT
MSBIN LSBIN
FRAME 1 FRAME 2
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