Memory and bus architecture RM0090
55/1422 Doc ID 018909 Rev 4
2.3.1 Embedded SRAM
The STM32F405xx/07xx and STM32F415xx/17xx feature 4 Kbytes of backup SRAM (see
Section 5.1.2: Battery backup domain) plus 192 Kbytes of system SRAM.
The STM32F42xxx and STM32F43xxx feature 4 Kbytes of backup SRAM (see
Section 5.1.2: Battery backup domain) plus 256 Kbytes of system SRAM.
The system SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state. The system
SRAM is split up into three blocks:
● 112 Kbyte and 16 Kbyte blocks mapped at address 0x2000 0000 and accessible by all
AHB masters.
● A 64 Kbyte block mapped at address 0x2002 0000 and accessible by all AHB masters.
(available on STM32F42xxx and STM32F43xxx). AHB masters support concurrent
SRAM accesses (from the Ethernet or the USB OTG HS): for instance, the Ethernet
MAC can read/write from/to the 16 Kbyte SRAM while the CPU is reading/writing
from/to the 112- or 64-Kbyte SRAMs.
● A 64 Kbyte block mapped at address 0x1000 0000 and accessible only by the CPU
through the D-bus.
The CPU can access the system SRAM through the System Bus or through the I-Code/D-
Code buses when boot from SRAM is selected or when physical remap is selected
(Section 8.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG
controller). To get the max performance on SRAM execution, physical remap should be
selected (boot or software selection).
2.3.2 Flash memory overview
The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
The Flash memory is organized as follows:
● A main memory block divided into sectors.
● System memory from which the device boots in System memory boot mode
● 512 OTP (one-time programmable) bytes for user data.
● Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Refer to Section 3: Embedded Flash memory interface for more details.
2.3.3 Bit banding
The Cortex™-M4F memory map includes two bit-band regions. These regions map each
word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word
in the alias region has the same effect as a read-modify-write operation on the targeted bit in
the bit-band region.
In the STM32F4xx devices both the peripheral registers and the SRAM are mapped to a bit-
band region, so that single bit-band write and read operations are allowed. The operations
are only available for Cortex™-M4F accesses, and not from other bus masters (e.g. DMA).
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