RM0090 Analog-to-digital converter (ADC)
Doc ID 018909 Rev 4 272/1422
11.4 Data alignment
The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 38 and Figure 39.
The converted data value from the injected group of channels is decreased by the user-
defined offset written in the ADC_JOFRx registers so the result can be a negative value.
The SEXT bit represents the extended sign value.
For channels in a regular group, no offset is subtracted so only twelve bits are significant.
Figure 38. Right alignment of 12-bit data
Figure 39. Left alignment of 12-bit data
Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in
Figure 40.
Figure 40. Left alignment of 6-bit data
11.5 Channel-wise programmable sampling time
The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
D7D8 D9 D6 D5 D4 D3 D2 D1 D0 D10 D11 SEXT SEXT SEXT SEXT
D7D8
D10 D11
Injected group
Regular group
0000
D9 D6 D5 D4 D3 D2 D1 D0
ai16050
D4D5
D6 D3 D2 D1 D0 0 0 0 D7 D8D9 D10 D11 SEXT
Injected group
Regular group
ai16051
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
D4D5
SEXT SEXTSEXTSEXT SEXT SEXT
Injected group
Regular group
ai16052
0 0 0 0 0 0 D5 D4 D3 D2 D1 D000 00
SEXT SEXT D3 D2 D1 D0 0 SEXT
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