RM0090 Universal synchronous asynchronous receiver transmitter (USART)
Doc ID 018909 Rev 4 782/1422
26.5 USART mode configuration
26.6 USART registers
Refer to Section 1.1 on page 47 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16 bits) or words (32 bits).
26.6.1 Status register (USART_SR)
Address offset: 0x00
Reset value: 0x00C0 0000
Table 122. USART mode configuration
(1)
1. X = supported; NA = not applicable.
USART modes USART1 USART2 USART3 UART4 UART5 USART6
Asynchronous mode XXXXXX
Hardware flow control X X X NA NA X
Multibuffer communication (DMA)XXXXXX
Multiprocessor communication XXXXXX
Synchronous X X X NA NA X
Smartcard X X X NA NA X
Half-duplex (single-wire mode) XXXXXX
IrDA XXXXXX
LIN XXXXXX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved
CTS LBD TXE TC RXNE IDLE ORE NF FE PE
rc_w0rc_w0rrc_w0rc_w0rrrrr
Bits 31:10 Reserved, must be kept at reset value
Bit 9 CTS: CTS flag
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared
by software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3
register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
Note: This bit is not available for UART4 & UART5.
Bit 8 LBD: LIN break detection flag
This bit is set by hardware when the LIN break is detected. It is cleared by software (by
writing it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
Note: An interrupt is generated when LBD=1 if LBDIE=1
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